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te c h w e l l, i n c. 1 r ev. a 0 2 /05 /20 08 TW8817 - digital lcd panel processor with built-in mcu, ntsc/p al/secam decoder and tcon techwell confidential. information may change without notice discl ai mer this d ocume nt pro v ide s t ech nical info rm ation f o r t he u s er. t e chw ell inc. rese rves t he ri ght to modif y the inf ormat ion in this doc ume nt as ne cessar y . t he cu st omer shoul d make s ure th at t he y have t he m o st rec ent data she et versio n . techw e ll in c. holds n o re spo n si bility f o r an y errors that may app ear in t his do cum ent. cust omers sho uld t ake a ppropriat e action to ensure their use of the product s does not inf r inge u p o n an y patent s. te chw e ll inc. re s pects valid p atent ri ghts of third partie s an d does n ot infrin ge upo n or a s sist ot hers to inf r ing e u pon su ch right s. http://
t w 881 7 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 2 re v. a 02 /05 /20 08 i n t r o duc t i o n .. ..... ..... ..... .... ..... ..... ..... ..... ..... ..... ..... .... ..... ..... ..... ..... ..... . 5 a p pli cati o ns . ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... .... ... ... .... ... .... 5 bu i l t- i n m i c r oc ontr o ll er . .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... 5 tft p anel s upport... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... ... . 5 on scr een d i sp l a y ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... ... . 5 i m age contr o l . ... ... .... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... 6 po w e r m anage m e n t ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... ... . 6 t i m i ng contr o l l e r ( t co n ) . .... ... .... ... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... 6 m i scell aneo us . ... ... .... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... 6 or de r i n f o r m a t io n .. .... ..... ..... ..... ..... ..... ..... ..... .... ..... ..... ..... ..... ..... ..... . 7 f unc t i ona l des c r ipti o n .. ..... ..... ..... ..... ..... ..... ..... .... ..... ..... ..... ..... ..... . 9 ov e r v ie w ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... .... ... ... .... ... .... 9 a n alog f r ont - e nd . ... .... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .. 10 vi de o deco de r ... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 10 y / c se pa r a t i on ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 10 co l o r dem o dul at i o n .. ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .. 10 au t o m a t i c chr o m a gai n contr o l .... ... .... ... ... .... ... .... ... .... ... .... ... ... .... ... .. 10 au t o m a t i c st anda r d det e c t i on .. .... ... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 11 co m pone nt pr o c es s i ng.. ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .. 11 di g it a l i nput s u p port .. ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .. 12 t f t pan e l sup p o r t ... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 12 d i t h e r i n g .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... .... ... ... .... ... .. 12 i m age con t r o l. .... ... .... ... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... .... ... ... .... ... .. 12 input i m age contr o l .. ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .. 12 i m age scali n g . ... ... .... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .. 12 co l o r spac e con v ersi on ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 14 on s c r een di sp l a y ... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 15 on c h i p osd f uncti ons ... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... .. 17 t w 8 817 basi c r e g i st er s e t t i n g fl o w for b u i l t - i n osd contr o l l e r . . ... .. 18 t w 8 817 al pha b l end i ng f o r o sd w i n d o w ... ... .... ... .... ... ... .... ... .... ... .. 23 mi c r o c on t r oll e r i n t e r f ac e .. ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .. 24 built-in mic r oco n t r o l ler . ........... .......... .......... .......... ........... .......... ....... ..... 24 po w e r m a nagem e n t ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 24 cl osed c a p t i oni ng and ex t e nd ed da t a s e r v ices .. .... ... .... ... ... .... ... .. 25 t e s t modes .. ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 29 t w 8817 packag e pi n di ag r a m .... ..... ..... ..... ..... .... ..... ..... ..... ..... .... 30 pi n de scri p ti o n . ..... .... ..... ..... ..... ..... ..... ..... ..... .... ..... ..... ..... ..... ..... .... 31 p a r a me tr i c i n for m a t i o n .. ..... ..... ..... ..... ..... ..... ..... .... ..... ..... ..... ..... .... 34 a c / d c e l ec t r i c a l p a r a me t e r s . ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 34 80- p i n t q f p p ack age mech an i cal dr aw i n g . ... .... ... .... ... .... ... ... .... ... .. 36 t w 8817 regi s t er summar y .... ..... ..... ..... ..... .... ..... ..... ..... ..... ..... .... 38 gene r a l . .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 38 decoder .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... .... ... ... .... ... .. 38 decoder ( c on t .) . ... .... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .. 39 lcdc ? i nput con t r o l . .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .. 40 lcdc ? i nput m e asur em e n t ... ... .... ... .... ... ... .... ... .... ... .... ... .... ... ... .... ... .. 40 lcdc - s c a l i n g .. .... ... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... .... ... ... .... ... .. 41 lcdc ? i m ag e ad j u st ment .. ... .... ... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 41 lcdc ? osd .. ... .... ... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... .... ... ... .... ... .. 42 lcdc ? di s p l a y con tr o l . ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 43 lcdc ? st a t us & i n te r r upt .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 43 lcdc ? p o w e r m anage m ent . ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 43 lcdc ? col o r e nhanc em ent .. .... ... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 44 lcdc ? etc ... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 44 lcdc ? g a mm a ... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 44 d a c . ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... .. 44 s s p l l ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... .... ... ... .... ... .. 44 ccfl co ntr o l .. ... .... ... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... .... ... ... .... ... .. 45 test cont r o l and g p o .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 45 tcon . ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 46 lcdc ? s ens e .. .... ... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... .... ... ... .... ... .. 47 test cont r o l . .... ... .... ... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... .... ... ... .... ... .. 47 m cu sf r regi st er .. ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .. 47 w 8817 r e gi s t e r s desc r i p t i o n . ..... ..... ..... ..... ..... ..... .... ..... ..... ..... .... 48 0 x 000 ? pr oduct i d code reg i st e r ( i d ) . ... .... ... .... ... .... ... ... .... ... .... ... .. 48 0 x 001 ? ch i p st at us reg i st e r ( cstat u s ) ... ... .... ... .... ... ... .... ... .... ... .. 48 0 x 002 ? i nput fo r m at (i nf orm ) ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .. 48 0 x 003 ? res e rv ed . ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 49 0 x 004 ? hsy n c de l a y co ntr o l .... ... .... ... ... .... ... .... ... .... ... .... ... ... .... ... .. 49 0 x 005 ? res e rv ed . ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 49 0 x 006 ? a n a l og co ntr o l regi st e r ( acnt l ) . ... .... ... .... ... .... ... ... .... ... .... 49 0 x 007 ? cr oppi ng regi st e r , h i gh ( crop_hi ) ... ... .... ... ... .... ... .... ... .... 49 0 x 008 ? v e r t i c a l delay re g i st e r , low ( vde l a y _lo) .... ... ... .... ... .... 49 0 x 009 ? v e r t i c a l act i v e reg i st e r , lo w (vactiv e_lo) . .... ... .... ... .... 50 0 x 00a ? hor i zont al del a y regi s t er , low (hd e l a y _lo ) . ... .... ... ... . 50 0 x 00b ? hor i zont al act i v e regi st er , low ( h a c t i v e _lo ) ... .... ... .... 50 0 x 00c ? c ontr o l r e g i st er i ( cnt rl1 ) .. .... ... ... .... ... .... ... ... .... ... .... ... ... . 50 0 x 00d ? c c con tr o l .. .... ... .... ... ... .... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... 50 0 x 00e ? w s s1 .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... 51 0 x 00f ? w s s 2 .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... 51 0 x 010 ? b r i g htness contr o l regi st er ( bri ght) .. .... ... ... .... ... .... 51 0 x 011 ? c o ntr a st contr o l r egis t e r ( c ontras t ) . .... ... .... ... .... 51 0 x 012 ? s h a r p n e ss cont r o l regi s t e r i ( sha r p ness) . .... ... .... 51 0 x 013 ? c h r o m a ( u ) ga i n regi st er ( s a t _u ) .... ... .... ... ... .... ... .... ... .... 51 0 x 014 ? c h r o m a ( v ) gai n reg i s t er ( s at _ v ) .... ... .... ... ... .... ... .... ... .... 51 0 x 015 ? h ue contr o l reg i s t er ( h u e ) . ... .... ... ... .... ... .... ... .... ... ... .... ... .... 52 0 x 017 ? v e r ti c a l peaki n g cont r o l i .. .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... 52 0 x 018 ? c o ri ng con t r o l reg i st e r ( c oring) .. .... ... .... ... ... .... ... .... ... .... 52 0 x 019 ? d e l t a rg b m o de and adc cont r o l regi s t er ... ... ... .... ... .... 52 0 x 01a ? cc/ eds s t at us regi st e r ( cc_ s t at u s ) . . ... .... ... ... .... ... .... 52 0 x 01b ? cc/ eds dat a reg i s t e r ( cc_d a ta) ... ... .... ... ... .... ... .... ... .... 53 0 x 01c ? st anda r d s e l e cti on ( sdt) .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... 53 0 x 01d ? st anda r d rec ogn i t i on ( s dtr) ... ... ... .... ... .... ... ... .... ... .... ... .... 53 0 x 01e ? co m p o n e n t v i deo f o r m at ( cvf m t ) ... ... .... ... ... .... ... .... ... .... 54 0 x 01f ? test cont r o l regi st er ( t est) . .... ... .... ... ... .... ... .... ... ... .... ... .... 54 0 x 020 ? cl a m p i ng g a i n ( c lm pg ) . .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... 55 0 x 021 ? i ndi v i d u a l agc ga i n ( i a g c ) ... .... ... ... .... ... .... ... .... ... ... .... ... .... 55 0 x 022 ? ag c ga i n ( a gcga i n ) . . ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... 55 0 x 023 ? w h i t e p eak th r e shol d ( p e a k w t) ... .... ... .... ... ... .... ... .... ... .... 55 0 x 024? c l am p l e v e l (clm pl ) ... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... 55 0 x 025? sy nc a m pl i t ude ( s y nct) . . .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... 55 0 x 026 ? sy n c m i ss count re g i st er ( m is s cnt) . . .... ... .... ... ... .... ... .... 55 0 x 027 ? cl a m p pos i ti on regi s t e r (p cl am p) .... ... .... ... ... .... ... .... ... .... 55 0 x 028 ? v e r ti c a l con tr o l i .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... 56 0 x 029 ? v e r ti c a l con tr o l ii ... ... ... .... ... .... ... ... .... ... .... ... .... ... .... ... ... .... ... .... 56 0 x 02a ? co l o r ki ll e r le v e l con tr o l .. .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... 56 0 x 02b ? co m b fi lt er c ontr o l . ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... 56 0 x 02c ? lu m a d e l a y and hf i l t e r cont r o l . ... ... .... ... .... ... .... ... ... .... ... .... 56 0 x 02d ? m i sce l l ane ous cont r o l reg i st e r i ( m i s c1) ... .... ... ... .... ... .... 57 0 x 02e ? m i s c e l l aneous contr o l reg i st e r i i ( m i s c2) ... .... ... ... .... ... .... 57 0 x 02f ? m i sce l l ane ous cont r o l i ii ( m i sc3 ) . ... .... ... .... ... .... ... ... .... ... .... 57 0 x 030 ? m a cr ov i s i on det e cti o n .... ... .... ... ... .... ... .... ... .... ... .... ... ... .... ... .... 58 0 x 031 ? c h i p stat u s ii ( c s t a t us 2 ) ... ... ... .... ... .... ... ... .... ... .... ... .... 58 0 x 032 ? h m o ni t o r ( h fref) .. .... ... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... 58 0 x 033 ? c l a m p m o d e ( c lm d ) . ... .... ... ... .... ... .... ... .... ... .... ... ... .... ... .... 58 0 x 034 ? i d de t e c t i o n c ontr o l ( nsen /sse n / psen/ w k th ) . . ... .... 59 0 x 035 ? cl a m p contr o l ( c lcntl) . .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... 59 0 x 038 ? a n t i - a l i a si ng fi lt e r an d decode r cont r o l . .... ... .... ... ... .... ... .... 59 f l at p a nel d i spl a y regi st e r s ... ... .... ... .... ... ... .... ... .... ... .... ... .... ... ... .... ... .... 60 0 x 040 t o 0 x 04f ? sc a l e r i nput cont r o l regi st er s .... ... ... .... ... .... ... .... 60 0 x 051 t o 0 x 05c ? i nput fo r m at m eas ur ement regi s t e r s . ... .... ... ... . 65 0 x 060 t o 0 x 06 b ? zoo m contr o l reg i st e r s . ... .... ... .... ... .... ... ... .... ... .... 67 0 x 070 t o 0 x 07 b ? i m a ge adj u st m ent reg i s t er s ... .... ... ... .... ... .... ... .... 69 0 x 07c t o 0 x 08 b ? b l ac k/ w h i t e s t r e t c h a d j u s t m ent reg i st e r s ... .... 70 0 x 092 t o 0 x 09d ? o s d cont r o l regi st e r s . . ... .... ... .... ... ... .... ... .... ... .... 71 lo w s p eed a d c an d m cu co n t r o l r e gi s t e r s ... ... .... ... ... .... ... .... ... .... 78 0 x 0c8 t o 0x 0ca ? lad c and m c u cont r o l regi st e r s .... ... .... ... ... . 78 0 x 0d0 t o 0 x 0d3 ? st a t us and i n t e r r upt reg i s t er s .... ... ... .... ... .... ... .... 78 0 x 0d4 t o 0 x 0d8 ? p o w e r m anage m e n t reg i s t er s . . ... .... ... ... .... ... .... 80 0 x 0da t o 0x 0df ? co l o r en hance m en t ... ... ... .... ... .... ... ... .... ... .... ... .... 81 0 x 0 e 0 ? et c ... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... 81 0 x 0f0 ? ga mm a . ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... 82 0 x 0f5 ? d a c con tr o l ... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... .... 83 0 x 0f6 ? d a c con tr o l ... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... .... 83 0 x 0f7 ? d a c con tr o l ... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... .... 83 0 x 0f8 ? d a c con tr o l ... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... .... 83 0x 0 f 9 t o 0x 0 f e ? s pr e a d s p e c t u m s y nt h e s i z er c o n t r ol r e gi s t er s 84 0 x 0ff ( o r 0x 1 ff) ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... ... . 84 0 x 130 ? c c fl contr o l i... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... 85 0 x 131 ? c c fl thr e s h o l d.... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... 85
t w 881 7 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 3 re v. a 02 /05 /20 08 0 x 132 ? ccfl c ontr o l ii. ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 85 0 x 133 ? ccfl p w m .. .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... .. 85 0 x 134 ? ccfl di m fr eque nc y ... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .. 85 0 x 135 ? ccfl di m c ontr o l .. ... .... ... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 86 0 x 136 ? p w m t op .. ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .. 86 0 x 137 ? spr ead s pect u m sy nt hesi z e r contr o l regi st e r s ... ... .... ... .. 86 0 x 140 t o 0 x 141 ? gp o .. ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .. 86 0 x 157 t o 0 x 15a, 0 x 1f0 t o 0 x 1 f 9 ? debu g reg i s t e r s . . .... ... ... .... ... .. 86 t i m i n g contr o l l e r conf i gur a t i on re g i st er s . .... ... .... ... .... ... ... .... ... .... ... .. 88 0 x 175 ? pol a ri ty and la t ch pu l s e contr o l reg i st er .... ... ... .... ... .... ... .. 88 0 x 176 ? g p io pi x e l count h i gh reg i st e r . .... ... .... ... .... ... ... .... ... .... ... .. 88 0 x 177 ? g p io pi x e l count lo w reg i st e r ... ... ... .... ... .... ... ... .... ... .... ... .. 88 0 x 178 ? g p io l i ne count h i g h reg i s t er ... ... ... .... ... .... ... ... .... ... .... ... .. 88 0 x 179 ? g p io l i ne count lo w reg i st e r .... ... ... .... ... .... ... .... ... ... .... ... .. 88 0 x 17a ? g p io f r am e count reg i st e r . ... .... ... ... .... ... .... ... .... ... ... .... ... .. 88 0 x 17b ? tcon an d del t a rgb m i sc. cont r o l regi st e r ... ... ... .... ... .. 88 0 x 180 ? ou t put m ode con t r o l reg i s t e r .. .... ... ... .... ... .... ... ... .... ... .... ... .. 89 0 x 181 ? d i spl a y con t r o l reg i st e r ... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .. 89 0 x 182 ? d i spl a y d i r e c t i on con t r o l regi s t er ... ... .... ... .... ... ... .... ... .... ... .. 90 0 x 183 ? contr o l sig n a l pol a r i ty se l e c t i on regi st er .... ... ... .... ... .... ... .. 90 0 x 184 ? contr o l sig n a l gener a t i o n m e t hod regi st e r ... .... ... ... .... ... .. 91 0 x 185 ? i n v e rsi on si gna l ope r a t i ng pe r i od r egi st er . .... ... .... ... ... .... ... .. 91 0 x 18a ? speci a l com p ani e s lcd m odu l e contr o l regi st er . .... ... .. 92 0 x 18b ? re v v ( t cp o lp) / revc ( tcpoln) cont r o l reg i st e r s.. 92 0 x 18c ? v e rt ic a l a c t i v e st art hi gh reg i s t er .. ... .... ... .... ... ... .... ... .... ... .. 92 0 x 18d ? v e rt ic a l a c t i v e st art low reg i st e r ... ... .... ... .... ... ... .... ... .... ... .. 92 0 x 18e ? ve r t i c a l ac ti v e e n d h i gh regi s t e r ... ... .... ... .... ... ... .... ... .... ... .. 92 0 x 18f ? v e r t i c a l ac ti v e end lo w reg i st e r . ... ... .... ... .... ... .... ... ... .... ... .. 92 co l u m n d r i v e r ch i p contr o l si gnals re l a t i v e regi s t e r s ... ... ... .... ... .. 93 0 x 190 ? pol a ri ty con t r o l h i gh regi st e r ... .... ... ... .... ... .... ... .... ... ... .... ... .. 93 0 x 191 ? pol a ri ty con t r o l lo w regis t e r . ... .... ... ... .... ... .... ... .... ... ... .... ... .. 93 0 x 192 ? load/ lat c h p u l s e st art h i gh reg i st e r .... ... .... ... ... .... ... .... ... .. 93 0 x 193 ? load/ lat c h p u l s e st art lo w reg i st e r . .... ... .... ... .... ... ... .... ... .. 93 0 x 194 ? load/ lat c h p u l s e w i dt h h i gh reg i st e r .. ... .... ... .... ... ... .... ... .. 93 0 x 195 ? load/ lat c h p u l s e w i dt h lo w reg i st e r ... ... .... ... ... .... ... .... ... .. 93 0 x 19a ? co l u m n d r iv e r s t art pu l s e h i gh regi s t e r . .... ... .... ... ... .... ... .. 93 0 x 19b ? co l u m n d r iv e r s t art pu l s e lo w re g i st er . .... ... .... ... ... .... ... .. 94 0 x 19c ? co l u m n driv e r st art pul se w i d t h h i gh reg i s t e r ... ... .... ... .. 94 0 x 19d ? col u m n driv e r st art pul se w i d t h low regi st e r .... ... .... ... .. 94 ro w d r i v e r ch i p cont r o l si gna l s re l a ti v e reg i s t e r s . ... ... .... ... .... ... .. 94 0 x 1a0 ? c l o ck s t a r t p u l s e hi gh reg i st e r ... ... ... .... ... .... ... ... .... ... .... ... .. 94 0 x 1a1 ? c l o ck s t a r t p u l s e l o w reg i s t er .... ... ... .... ... .... ... .... ... ... .... ... .. 94 0 x 1a2 ? c l o ck s t a r t p u l s e w i dt h hi gh reg i s t e r .. ... .... ... .... ... ... .... ... .. 94 0 x 1a3 ? c l o ck s t a r t p u l s e w i dt h low reg i s t er ... ... .... ... ... .... ... .... ... .. 94 0 x 1a4 ? ro w st a r t p u l s e h i gh reg i s t e r . ... .... ... .... ... .... ... ... .... ... .... ... .. 95 0 x 1a5 ? ro w st a r t p u l s e lo w reg i st er .. .... ... ... .... ... .... ... ... .... ... .... ... .. 95 0 x 1a6 ? ro w st a r t p u l se w i dt h hi gh reg i st er .... ... .... ... ... .... ... .... ... .. 95 0 x 1a7 ? ro w st a r t p u l s e w i dt h low r e g i s t e r .... ... .... ... ... .... ... .... ... .. 95 0 x 1ac ? ro w ou t p u t e nab l e h i gh reg i st e r . ... .... ... .... ... .... ... ... .... ... .. 95 0 x 1ad ? ro w ou t p u t e nab l e lo w regi st e r.. ... .... ... .... ... ... .... ... .... ... .. 95 0 x 1ae ? ro w ou t p u t enabl e w i dt h hi gh regi st er .... ... ... .... ... .... ... .. 95 0 x 1af ? ro w o u t p u t enab l e w i dt h lo w regist er . .... ... .... ... ... .... ... .. 96 0 x 1b0 ? panel t y pe se l e c t regi st e r . .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 96 anal og sens e bl o ck regi st e r .. .... ... ... .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 96 0 x 1b1 ? ana l og s ens e bl o ck cl oc k gener a t i on r egi st e r . .... ... .... ... .. 96 m cu sf r regi st er .. ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .... ... .... ... ... .... ... .. 97 0 x 9a ? m c u bank s e l e ct reg i st e r .. .... ... .... ... ... .... ... .... ... ... .... ... .... ... .. 97 0 x 9b ? m c u m i sc. contr o l reg i st e r .... ... .... ... ... .... ... .... ... .... ... ... .... ... .. 97 0 x 9c ? m cu ex t e r n a l ti m e r c l o c k 0 div i de r h i gh regi st er.. .... ... .. 97 0 x 9d ? m cu ex t e r n a l ti m e r cl o c k 0 div i de r low regis t e r .. .... ... .. 97 0 x 9e ? m c u ex te r n a l ti m e r cl o ck 1 div i de r hi gh regi st er .. .... ... .. 97 0 x 9f ? m c u ex t e r nal t i m e r cl o c k 1 div i der low regi st er ... .... ... .. 97 0 x 93 ? m cu ex t e r n a l ti m e r cl oc k 2 di vi der hi gh regis t e r .. .... ... .. 97 0 x 94 ? m cu ex t e r n a l ti m e r cl oc k 2 di vi der low r e g i st er ... .... ... .. 97 co p y ri g h t no t i c e .... ..... .... ..... ..... ..... ..... ..... ..... ..... .... ..... ..... ..... ..... .... 98 t r adema r k a c k n o w l e d g ment . ..... ..... ..... ..... ..... ..... .... ..... ..... ..... .... 98 di sc l a i m e r ..... ..... ..... ..... .... ..... ..... ..... ..... ..... ..... ..... .... ..... ..... ..... ..... .... 98 lif e s uppo r t p o li c y ..... .... ..... ..... ..... ..... ..... ..... ..... ..... .... ..... ..... ..... .... 98
TW8817 di g i t a l lcd p anel pr oce s sor with vide o de code r, mcu and t c o n te ch we ll, i n c. 4 rev. a 02/05/2008
TW8817 di g i t a l lcd p anel pr oce s sor with vide o de code r, mcu and t c o n te ch we ll, i n c. 5 rev. a 02/05/2008 introduction ap p licat i o n s - mobi l lcd t v s - r e ar se a t en t e r t a i nm en t - por t ab l e dv d, pmp a n d hmd ( h ea d mo unt di sp lay ) featu r e s the TW8817 is a l o w co st high q u al it y tft pan el co n t r o l l e r w i th embedd ed nts c /pa l /seca m tv deco der. it incorpo r at es all the features re q ui r ed to create multi - pur p o se low cost lcd t v s y st ems in a si ng l e packa g e . it contain s a l l the ci rcuit s req u ir ed to adapt sta n d a r d nt s c /pal/ s eca m analog tv i nput si gnal s fo r di spl a y o n va r i ou s tft lcd pan e l t y pe s. an integ r at e d timing co nt r oll er all o w s d i re ct in te rf a c e with d i gital l cd panels. its ve rsatile analog in p uts allow cvbs, s - vid eo, si gnal to be co nnected simultan e o u s ly . o t h e r features incl ude: hi gh qualit y a dapt i v e 4 h comb filter, do w nscalin g to q v ga ou tput re so l utio n , i n te r l aced and pr o g ressi v e i t u 656 i n p u t support, 2 d de-i n t er l a c er and panar o m i c scal er, and multi - wi n dow progr ammalb e o s d. i t a l s o i n c l u d e s im ag e en h a n ce me n t f u n c t i on s s u ch as b l a c k and w h ite str e tch, 2 d p e a k i n g , ct i, and favo r i te co lor enhan ce ment to further impr o v e p i ctu r e q u al it y . it al so i n cl udes cost sa ving fea t u r e l i k e ccfl co n t r o ll e r , ch arge pu mp b o o s ter and progra mma ble p anel offset co n t r o l . in ad d i ti on, tw8 817 h a s bui lt- i n microcon t r ol l e r w i th exte rn a l spi inter f ac e. ana l og v i d eo de co d e r n t sc ( m , 4. 34 ) a n d pa l ( b , d, g , h , i , m , n, n c o mbi n ati o n), pal (60 ) , sec am w i t h au tom a t i c fo r m at de te cti o n ? adv anc ed sy nchr oni za tio n p r oc essi n g f o r vcr tr ick pl ay si gnal ? t w o 10 - b it adcs and ana l og c l amp i ng c i r c u i t. ? bu i l t - i n ana l og an t i -a l i a s i ng f i l t e r ? full y pr og ra m m a bl e st a ti c g a in o r aut o m atic g a in c o ntr o l f o r the y or c vbs channel ? pr ogrammabl e w h ite peak c ontro l for the y or c vbs c h annel ? soft w a r e s e l e c t abl e a n a l o g i n p u ts allow s any of t h e f o ll ow i n g co mbi n a t io ns : 3 c o m pos it e vi de o 1 s - vi d eo ? 4-h ad ap ti v e c o mb f ilt er y /c s epar ati on ? pal d e l a y line f o r col o r ph as e e r r o r c o r r ec tio n ? digi t a l p l l fo r b o t h col o r an d h o r i zo nt al l o c k i n g ? pro gr a m m abl e hue , br i g h tn ess , s at ur a t i on , c ontr as t, s ha r p ne ss, gam m a co nt ro l, and no ise supp re ssi on ? a u t o mat i c co lo r c o n t ro l an d co lor ki ll e r ? det ec ti on of l ev el of c opy pro te c tio n ac c or di n g to m a cr ov isi o n s t anda rd buil t-in m icrocontroll e r ? supp or t ex ter n al spi i n t e r f ac e ? su p po r t i2 c mas t er in te rf ac e w i t h g p io ? supp or t up t o 4 mcu gp io ? supp or t uar t i n ter fa ce w i th g p io ? supp or t ir o r i n ter r u p t w i th gp i o t ft p ane l s upp or t ? supp or ts a w i d e v a r i ety of d i gi t a l sin g l e pix e l act i ve m a tr ix t f t pa ne l s ? supp or ts 3 , 4, 6 bi ts p e r pix e l f o r m at on scr e en di splay ? built -i n osd c o ntr o l l er w i th i n t e gr ate d c h ar act e r r o m an d pr o g r a m m a ble ram f o nt . ? mul ti- w i ndow o s d s u pp or t w i th col o r pall e t ? suppo r t o s d over l a y wit h alpha blend i ng te chwell TW8817 audio am p ntsc / pal / secam tuner
TW8817 di g i t a l lcd p anel pr oce s sor with vide o de code r, mcu and t c o n te ch we ll, i n c. 6 rev. a 02/05/2008 imag e co n t r o l ? prog ramm ab le hu e, b r igh t n e s s , s atu r a t i on , c ontr a s t ? sh ar pnes s c o nt rol w i th v e r tic al p eak i n g ? prog ramm ab le co lo r tran s i e nt i m p r o v em en t con t r o l ? bui l t- i n d e- i nt erl aci ng en gi n e ? i ndep en de nt r g b ga i n and o f fse t con t ro ls ? pa no r a m a / w a ter - g l a ss sc ali ng ? y c bcr hu e ad j ust m en t ? prog ramm ab le ga mma co r r e c t i on tab l e s po w e r ma na geme n t ? su pp or ts pa nel p o w e r s e que nci n g. ? sup p o r t s d p m s fo r mon i t o r p o w e r manag eme n t. ? 1 . 8 / 3. 3 v ope ra t i on ti m i ng co nt r o l l e r ( t co n) ? su pp or t pr o g r a m m a b l e i n t e r fa c e s i g nal s fo r c o n trol c o lum n (sou r c e ) dri v er / ro w ( gat e ) d r ive r mi sc ellan eou s ? supp or ts 2 - w i r e se r i al b us in t erf ac e ? spr e ad s p ectr um p ll ? c c f l c ont ro ll e r ? led c o nt r o ll er ? low -s pee d ad c f o r k e y scan ? pro g r a m m abl e pan el vco m o ff s et c o ntr o l ? 5v t o l e r a nt i /o ? pow er- d ow n m ode ? t y p i c a l po we r con s umpt io n l e s s th a n t b d ? si ng l e 27m h z c r y s t a l ? 80- pin t q f p p a cka g e ? bui l t- i n y c bc r t o r gb c o l o r s pac e c o nv er te r ? bl ack / w h it e str e tc h ? prog ramm ab le f a v o r i te c o lo r e nha n c emen t
TW8817 di g i t a l lcd p anel pr oce s sor with vide o de code r, mcu and t c o n te ch we ll, i n c. 7 rev. a 02/05/2008 order information packa ge de scri p ti on part # name description pins body size (mm) TW8817 tqfp thin quad flat package 80 12x12
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 8 r ev. a 0 2 /05 /20 08 cin 2x analog front end mux sync processor 4h adaptive comb filter chroma demodulation yuv processing mux color matrix line buffers scaler /deinterlacer image enhancement gamma / dither panel timing generator alpha blending osd host interface 2 wire serial bus input format measurement tcon fpr[7:0] mux yi n0 yin1 fpg[7:0] fpb[7:0] fpv s fphs fpde fpclk fppwc fpbias mc sd a mc scl mc si a tcon signals spread spectrum pll yout data registers spi interface mcu mc u e n p 2 .0 ~ p2 .7 mc u s d a mc u sc l sp i _ d o sp i_ d i spi_csn spi_clko ccfl controller low-speed adc adin0 adin1 f igu r e 1 tw8 817 f lat panel tv/ m oni to r c ontrol le r fu nction al b lock diagram
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 9 r ev. a 0 2 /05 /20 08 functional description overview t e ch we ll?s tw 8817 f l a t p a ne l t v / m o n i t o r co n t r o ller is a lo w co st h i g h qua lit y t f t pan el c ont ro ller wit h e mbe dd e d nt sc/ pal/ s e c a m t v deco der . t h is un iq ue le v e l o f mixed sign al in te gra t ion e nab les the p ane l to b e used as a stan d-alon e ana lo g t v . s epar a t ed dig i tal in pu t s allo w it to be u s e d a s a h i gh qu alit y com put er mon i tor. i t in corpo r a t e s e a s y - t o - ope rat e an d p o w er fu l f eat ures in a single p a ckag e f o r mu lti- p urpos e p c d i s pla y an d l cd/t v ent erta inm en t s y s te m s . th e t w8 817 c ont a i ns a ll t h e log i c re q u ir ed to co nve r t s t a n d a rd t v , dt v, and pc m onit o r signa ls t o the d i g i t a l con t rol a n d d a t a s i g nals r equ ire d to dr ive var i ous tft pa nel t y p e s . i t s uppor ts t f t p a n e l resolu tions up t o wx g a . t he ch ip ac cep ts cv bs (comp osite) a n a l o g in p u t or s- vid eo an a l o g in pu t, u p t o two cv bs in p u ts or one s-v i d e o in pu t. t h e int egra ted ana log front -en d co nta ins 2 a d cs wit h c l a mping c i rcu i t s a n d auto ma t i c g a in con t ro l ( a g c ) circu i t t o m i nimize exte rna l c o m ponen t co unt . it e m plo y s a 4h , 5-lin e a dapt ive com b f ilt e r and p r o p r i e tar y y/ c pr o c essing te chno lo g i es to p r odu ce e x c ept iona ll y h i g h q u a lit y p i ct u r es. fig u re 2 t w 8817 flat panel t v /mo n ito r c ontroll e r s y st em block d iag ram di g ital lcd panel ntsc / pal / secam tuner techwell TW8817 audio a m p
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 10 r ev. a 0 2 /05 /20 08 t he ch ip 's int e rna l lo g i c s y n c h r o n i zes t h e pane l f r a me r ate to t h e inc o m i n g inp u t frame ra te . a h i g h q u a lit y imag e-scaling e ngine is used to co nver t th e lo wer re solu t i on fo rma t s or h i gh r e so lu tion dt v fo rm a t s t o th e o u tpu t pa ne l reso lu tion . a n in ter nal de- in terlac i n g e ngine also allo ws in ter laced vide o t o b e su pp o r ted . o n scr e en d i spla y is sup ported t h r oug h on -ch i p o s d rom / r a m combination for maximum flex ibi lity . a c l o s e d cap t ion dec oder is b u ilt in . t he tw 8 8 17 a l so accep t s a 16 bit digita l rg b in p u t f r om e x t e rn a l digit a l s o u r ce s f o r u s e a s na vi gat i on m o nit o r. i n a ddit i on, it a c c ept s 8/ 1 6 bit s d i git a l y c b c r in pu t f o r dire ct con nect i on wit h o the r d i g i t a l sour ce like mpeg d e co de r. t h e t w88 17 also sup por ts tft p a n e l powe r seq uenc in g, d p ms ( v e sat m d i s p la y p o we r man age me nt s i g na l in g) sign a l in g an d powe r ma nag eme n t. t he con tro l in ter face is a 2 - wir e se ria l bu s in ter fa ce . t he t w881 7 core o p e r a tes a t 1 .8 v, th e io a t 3 . 3 v an d packag ed in a 80 -p in tq fp packag e . an alog front - e nd t h e a n a l og fro n t - e n d con v er ts ana log vide o sign als t o the re qu ired digit al for m a t. t h ere are th re e an a l o g cha n n e ls. e a ch ch an nel cont ains cla m pin g circu i t, ag c c i rcu i t, a n ti-alias i n g filte r a nd h i gh pe rfo r m ance ad cs to mi n i m i ze the e x terna l compo n e nt u s e d . t her e are t o t a l 3 analog inpu ts for ma xim u m flexib ilit y . so ft w are s ele cta b l e an alo g inp u ts allow many pos sib l e inp u t c om bi nat i on s b et w een com po s it e vi de o , s- video . vid eo decode r t h e vide o de co der o f t w 8817 cons ists o f s y n c h r on iza t ion , y / c se pa ra tion , co lo r dec oding an d com pone n t pro c essing c i rcuits . t h e s y n c p r oc ess o r co nta ins d i g i ta l pha se - l ock ed-loo p an d decision log i c to ach i ev e r elia ble s y n c de te ct io n in s tab le s i g nal a s we ll as in n o n-st a ndar d s i gnals suc h as th ose fr o m v c r p l a y b a c k . it a l so provide s e x ce pt io nal we ak signa l pe r f o r man c e . y/c separa t i on t h e y / c s e p a r a t i o n b l ock p r o v ides the luma / chr o ma sep a ra t i on fo r th e co m p osit e vide o. f o r nts c a nd p a l stan da rd s i gna ls , th is is ach i e v e d th roug h high qu ality 5 - lin e ad ap ti ve co m b f ilt er. fo r s e c a m st anda rd signa ls, ada p t iv e no tch / b a n d -pass filt er is emp l o y e d . d u e to t h e lin e bu ffe r use d in t he co mb filt er , t here is alwa y s t w o line s proc essing d e l a y in t he o u tp ut im a g e s no m a t te r what st an da rd or f ilt e r o p t io n is ch osen . i f no tch / b a n d - p a s s filter is se lect ed, t h e ch a r a c te ri st i cs of t he f ilt e r s are sh ow n in t he f ilt er curve s e cti o n. col o r de m odul ati on t he co lo r dem odu la tion for nt sc a n d p a l sta nda rd is d on e b y q u adr a t u r e mixing the chr o m a sig na l to th e b a se ba nd. t he su b-ca rrie r sig n a l f o r u s e in th e co lor dem od u l a t o r is ge nera ted b y d i rect d i g i t a l s y n th e s is p ll th at lo cks o n t o th e inpu t sub - ca rrie r re f ere nce ( c olo r bu rs t ) . th is a r ra ng eme nt a l lows an y sub- stand ar d o f nt sc an d p a l t o b e dem odu la te d easil y . f or the pa l s y s te m , the pa l id is ide n tifie d to a i d the pal co lor d e m o d u l atio n . t he s e ca m dem odulat ion p r oc ess is d one t h rough f m de mod u la tion a nd d e -empha sis f ilt e r . t he chro ma ca r r i er f r e q u enc y i s ide n t i fie d and u s e d t o cont ro l t he se cam co lor dem od ul a tio n . aut o m a t i c c h roma g a in c o ntro l t h e au toma t ic chr o ma ga in co ntro l (acc ) co mpen sat e s for r educ ed amp l it ude s ca use d b y hig h - fr eq uenc y lo ss in v i d e o sign al. t h e ra nge o f acc con t ro l is ? 6db to +2 4d b. for lo w c o lor am plitu d e signal s , bla ck and w h ite v ideo, or ver y nois y signal s, the c o lo r output w ill be ?killed?. the thr es hold has p r o g r a mmed h y s t e r es is to pr eve n t oscilla t ion of the color k iller oper at ion . t h is f unction ca n b e d i sab l ed b y p r o g r a mming a low th resh old va lue .
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 11 r ev. a 0 2 /05 /20 08 au tom a ti c stan dard d e te cti on t he t w 88 17 h a s b u ild - i n au to mat i c stand ar d d i scrim i na ti on c i rcu i t r y . t h e c i rcu i t use s b u rst-ph ase, bu rs t - fr eq uenc y a nd f r a m e ra te t o id en tif y nt s c , pal or se ca m co lo r sig na l s. t he s tan da rds that ca n b e id ent ified are nt sc (m), nt s c (4 .4 3), p a l (b , d , g , h , i) , p a l ( m ) , p a l (n), p a l ( 6 0 ) an d secam (m ). e a ch sta ndard can be inc l uded o r e x clu d e d in the s t a ndar d recog n itio n proce s s b y so ft war e c ont ro l. t h e id ent ified stand ar d is in dica t e d b y t h e s t a nda rd s e lection ( s dt ) re g i st er. a u to m a tic st andar d det ec tio n can be ov err i dd en b y so ft wa r e con t ro lle d sta ndar d se lec t io n . t w 881 7 supp or ts a ll commo n v i d eo for m a ts as s h o w n in t a ble 1 . t h e vide o d e cod e r n e e d s t o be p r o g r a mmed app ropr ia te l y f o r e a ch of th e c o mposit e vide o in pu t f o rmat s. format lines fields fsc country nt s c - m 52 5 60 3 . 58 m h z u.s., many others n t sc-j apa n (1 ) 52 5 60 3 . 58 m h z japan pa l- b , g 62 5 50 4 . 43 m h z many pa l- d 62 5 50 4 . 43 m h z china pa l- h 62 5 50 4 . 43 m h z belgium pa l-i 62 5 50 4 . 43 m h z great britain, others pa l-m 52 5 60 3 . 58 m h z brazil pa l- cn 62 5 50 3 . 58 m h z argentina se cam 62 5 50 4 . 40 6m hz 4.250mhz fr a n c e , eas ter n eu ro pe, m i ddle eas t , r u ssi a pa l-60 52 5 60 4 . 43 m h z china n t s c ( 4 .4 3 ) 52 5 60 4 . 43 m h z transcoding n otes: (1) . ntsc- j a p a n h a s 0 ir e se tup . co mponent proce ssing th e tw 8 81 7 a dj u st s b r ig ht ne s s by addi n g a p r o g r am mab l e valu e ( i n re g i st e r b r i g h t ne ss ) t o th e y sig n al. i t adju s t s t he pi ct u r e co nt ra st b y chan gin g t he gai n (i n r egi st er c o n t ras t ) of t he y si gnal . t he t w88 17 als o prov ides a sha r pness co n t r o l f u n c tio n th ro ugh c ont rol r e g i st e r s . it provides the co n t r o l in 1 6 steps up to + 12db . t he cen ter f r eque ncy o f th e enh anc em ent curve is s e lectab le by s o f t w a r e co ntr o l . i t a l so provides a h i g h f r equen c y co rin g f unc tion to mi nim i ze th e a m p lifica t io n o f h i gh freq ue nc y n o i se . t o fu r ther e n h ance the imag e, a p r o g ra mm a b l e ver t ic al pea king f unc tio n is pro v ided fo r up to +6 db o f e nhan ce m e n t . t h e t w88 17 provides th e color t r ans ie n t impr ove m en t f unc tio n to fu r ther en ha nce t h e imag e q ualit y . th e cti en ha nce t h e co lo r ed ge t r an si ent w i tho ut a n y hue d i st ort i o n. t h e co lo r sa tu rat i on can be adjus ted b y cha n g i n g the ga in o f cb an d cr s i g n a l s fo r a ll nt sc , pa l a nd s e c a m for m ats . t he cb a n d cr ga in can b e adju s t e d ind e p e n d e n t l y f o r flexib ilit y . t a bl e 1. vid e o in p ut format s supported by the tw8 8 1 7
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 12 r ev. a 0 2 /05 /20 08 dig ita l input supp ort in add ition t o a nalog inp u t s , th e t w8 8 1 7 h a s a 16-b i t digit a l in put fo r y c b c r or rgb d a t a . e x t e rna l a d cs can be used t o make th e c o n v er sion f r om a n a l og comp onen t in pu t s to d i gita l y c bcr o r rg b to supp or t of dt v 48 0p , 72 0p, an d 1 080i, or p c vg a in p uts f r o m q v g a t o wx g a . t h e inpu t in cludes v s y n c , hs y n c, pix e l cl o c k a n d t h e opt i o n a l dat a q u a lif ie r. fo r int e r la ced vid e o , t h e ti m i n g re lat i on sh ip b e t w een v s y nc a nd h s y n c d et erm ine t he f i eld f l ag . t he o p tion a l da ta qua lif ier is nee de d wh en in pu t vide o da ta is not con t inuou sly va lid with in a line . tft panel support t h e t w 8817 s u ppor t s v a r i eties of di gital active matr ix t ft panel s w ith one pix e l per cloc k mode. it sup por ts p a n e l wit h re so lu t i on u p t o w x g a res o lut i o n . di th eri ng if th e color dep th o f t he in pu t d ata is la r g e r t han th e lcd pa ne l colo r d e p t h , t h e tw 8 8 1 7 c an b e se t t o dither the im age. up to four bits of apparent col o r d ept h c a n be added w ith the internal di t h er in g ability of the t w 8817. t h i s all o w s lcd panel s w i th 4, 6 or 8 bits per col o r per pi x e l to di spl a y up to 16.8 milli on colors and l c d panel s w ith 3 bi t s per color per pixel to c an displ a y up to 2.1 m illi on color s . t he t w88 17 uses bo th spat ial an d fra m e m odu la tion d i t h ering . w h e n d i the r i n g wit h t h e le as t signif i can t 4- b i ts o f in put da ta the t w881 7 uses sp a t ia l m odula t ion wit h 4x4 b l ocks o f p i xe ls. wh en d i ther ing with th e le ast sig n i fican t 1 t o 3 bit s of inp u t d ata , t h e t w88 1 7 us es b o t h s p a t ia l m o du la tion wit h 2 x 2 pixe l b l ocks, a nd fr ame modu la tion . im age control input imag e con t ro l t he inp u t crop p i n g co n t r o l p r ov ides a wa y fo r pr ogr am ming the active d i sp la y win dow re gion fo r t h e selec ted inpu t v i d e o or g r a phic. in th e n o rm al o pera t io n , t h e f i rst active line s tart s with th e vs y n c sig nal. th i s an d ve rti c a l a c t i ve le ng t h re gi st er set t i ng a r e use d to de term i n e t h e active ver t ica l win d o w . t h e ac tive p i xe l star ts hs y n c. t h is a n d th e h o r i z on ta l a c tiv e w i dt h regi st e r are us ed t o de te rm in e th e a c t i ve hori z ontal w indow . t h e ver t ical w indow i s pr ogra mmed in line increm ents. t he hori z ontal w i ndow is pr og ra m m e d i n one p i xe l in c r e m e n t s fo r si ngl e pixe l in pu t mod e o r t w o pixe ls i n cre m e n t s f o r do ub le pix e l s input mode. if data qu alif ier i s used, then only qualifi ed pi xels w ill be c o unted in the w i ndow s i z e . image sca l ing t h e t w88 17 in ter nal im a ge-sc aling en g i n e o p e r a tes in se ver a l mod e s. th e f i rs t is the b y pa ss m o de . no imag e sca lin g is do ne in t h is mo de. t h e num ber o f act i ve ou tpu t lines p e r fra m e and t h e nu m b er o f ac tive o u tpu t pixe ls per line are id e n t i ca l t o t h e inp u t ac tive lin e s and pixe ls , re sp ec tivel y . t h is mo de is b e s t use d fo r disp la y i n g compu ter gr aphic a t pane l's n a t ive resolu t i on . b y d e f a u l t, t h e in pu t a c t i ve win d o w is zo o m e d up to th e fu ll scr e e n f o r d i sp la y . t h is is use d f o r non- in ter la ce d da ta like p c gr aph ics or progr e ssive sca n v i de o. t he ve rtica l a nd h o rizo nta l ma gn ifica t ion ra tio can b e ad ju st e d ind epen den tl y . s i n c e th e t w 88 17 has n o fr ame buf fe r, th e zoo m ra tio an d ou tput c l ock r ate s h ould be c oordi nat ed app r opr iatel y to av oid i n ter nal buffer ov er-run. t h e t w 8817 has a de-inter l a c i ng mode to pr oc es s i n ter l a c ed vi deo inputs. in thi s m o de, ev er y input field is zo om e d to t he f u ll o u t p u t f r am e re sol u t i o n . a p r op riet a r y lo w ang l e co m p en sati o n ci rcu i try adap tiv e ly corr ect s t he inte rp o l a t ion pr ocess t o r e su lt in smoo th v i deo re nd ering . th e de-in terlaced fields can a l s o be p r o p e r ly co mpen sat ed to hav e fie l d s alig ned co rrec t l y to a v o i d an y a r tifa c t s. t h e o ffse t can be p r o g r a mmed to prov id e m a ximu m fle x ib ilit y.
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 13 r ev. a 0 2 /05 /20 08 t he h orizo n tal sca ler c an be p r o gr a m m e d t o p erfor m panor amic or wa te r- g l ass sca l in g for d i sp la y i n g 4 :3 in put o n a 16 :9 d i s p la y . ima g e enh anc em en t proc ess i ng a d aptiv e bl a ck/ w h i t e s t re tc h t h is fea tur e is to e x pan d d y n a mic ran g e of th e inpu t im ag e , which create s m o r e vivid im age impressio n . fa v o rit e co l o r enhancem ent t h is fea tur e allo ws e n h anceme n t of color th at is no t p r im a r y co lor. up to t h re e user pro g ramm able co lors can be se l e cted fo r e nhanc eme n t . the ga i n f o r each col o r s e lected i s a d j ust able f o r ma ximu m f l exi b ilit y . it y i e l ds r i ch an d c o lorfu l vide o imag es.
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 14 r ev. a 0 2 /05 /20 08 disp lay ti ming t he t w88 17 is ope ra ted in fra m e s y n c mo de o n l y wit h no e x te rn a l m e m o r y r e quired . i n th is mo de, th e o u tpu t f r a m e ra te is s y n c h r o n iz ed with t he inpu t fram e rat e . s i nce t here is n o frame buf fe r, t h e d i s p la y clock frequen c y and zoom ratio hav e to be pr oper l y s e lec ted to m a t c h the panel resol u tion. t h e internal sca ling e n g ine a b sor b s the dif f e r ence betwe e n th e inpu t lin e ra te an d ou tpu t line ra te as well a s the differ enc e bet w een the i n put pi xel rate and output pixel rate. th e f r e q u e n c y of t he flat p a nel clo ck ou t p u t pi n c an b e con t r o lle d by an int e r na l sp re ad sp e c t r u m p ll o r b y a n e x t e rn a l osc illa tor co nnec ted to th e pl lck i p i n . wh en the in ter nal fre q u e n c y m u lt ip lier is b e i n g u s e d , t he frequ en c y o f th e fla t p ane l clo ck o u t put signa l is d e t e r mine d b y f p l l va lu e a nd th e po st di vid er. fr equenc y fp clk = 1 0 8 m hz x f p ll 2 17 x 2 pos t col or sp ac e con v ersion t he t w88 17 h a s b u ilt-in y c bcr t o rg b co lor s p ac e conv ert e r f o r th e in terna l dec oder o u t p u t a nd the digit a l y c bcr input. t h e i n ternal ci rc uit w ill c l am p the y data v a l ue to the r a nge of 16 to 235 for an 8- b i t in put . i t a l so cla mps the cb cr dat a value to t h e range o f 16 to 240 in c o mp lia n ce with t h e ccir60 1 st anda rd . fp hs fpde fpr/g/b fp c lk fphs fp de fpv s figure 3 flat panel output signals
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 15 r ev. a 0 2 /05 /20 08 o n screen d i splay t h e t w 8817 sup port s bu ilt -in o s d co n t roller with int egra ted characte r ro m an d pr og ra mmab l e r a m fo n t. t he o s d d i sp la y is inde pe nden t o f t he inpu t active win d o w se tt ing or t h e sc a l ing ra t i o. the on-chip osd controller is a character-based controller. the pre-defined character or graphic bit map is stored in the internal rom. there are a total of 202 built-in fonts. each character is 12 pixels wide by 18 pixels high. the characters can be displayed on the screen in four user defined window locations of any size from 1 to 256 characters. the spaces between c haracters are also programmable. there is a limit of 256 characters that may be displayed on screen at one time in all windows combined. the attributes of each window can also be set to give it a shadow effect or 3-d effect. in addition, the characters can be expanded by a factor of 2,3 or 4 in vertical or hori zontal directions and have the italic effect, under line effect on a character by character basis.
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 16 r ev. a 0 2 /05 /20 08 figure 4 fon t ro m c h ara c te r s and a d d r e sses
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 17 r ev. a 0 2 /05 /20 08 o n c h i p o s d func t i o n s % fo nt ro m : 20 2 c h a r acte rs - cap i ta lized en glis h alp ha be t, numbe r s, mon i tor c omm on co n trol i m a ge , s p e c ia l a l p h ab e t char acters % fo nt sra m : ma x 7 5 user pro g ram m a b le sing le co lor fo nt or m a x 2 5 user prog ramm a b le m u lti-color f o n t sup por ts (2 048 x8 s r am) s i n g le co lor / mu lti-c o lo r fon t s co mbine nu m b e r : def ined b y u s er . ( mu l ti-c olor s t a r t a d d r ess ca n c hange . ) % cha r act e r reg i st er s r am : 25 6 locat ion (8- b it fo n t ad dress + 1 1 -b it char act e r att r ibu t e , 256 x2 0 s r am) % characte rs c harac ter c olor : 16 co lo rs c harac ter backgro und co lor : 16 co lors c harac ter blink i n g : e n a b le /disab le , 1 hz b lin k i ng fre quenc y c harac ter ita lic e ffec t : en able / disa ble c harac ter u nder li ne effect : enabl e/dis a ble (mu l t i o s d win d o w displ ay c ase : ch ip ha s a l i m i t a tion) c harac ter spac e : b oth h a n d v p r o g ram m a b l e b y n u m be r o f p i xels q u ick cha r acte r c ha n g e in w i n dow : p r o g r a m m a ble sta r t addr ess an d bu ffe r s i ze p r og rammab l e o s d color p a let t e su ppor t r e -des ig n e d o s d fon t sup p o r ting s tand ard a l p ha-numer i ca l char acter s e t % w i ndo ws n umbe r o f w i n do w s : 4 i nde pe nd ent w i nd ows wi nd ow colo r : 16 co lo rs wi nd ow zo om : 2, 3, 4 tim e s zo om by d o t nu mb e r , h/v se pa rat e z o o m in g con t r ol wi nd ow po sit i on : p r og ra m m ab l e h d i re c tio n : 1 - p i xe l per s t e p , v d i r e c tio n : 1-l i n e per ste p w i n d o w s i ze : bo th h and v p r o g r a mm able b y nu mb er of cha r ac ter s w i n d o w b o r d e r in g / sh a d o w in g ef fect : 4 ind epen de n t w i n d o w s en ab le/d isab le co ntrol wi nd ow alp h a blen d i n g con t r o l : 4 in de pe nd en t win dow s co nt rol 16 dif fer ent c o lo r f o r a l p ha blen d i ng sup p o r t(4- bit co n t ro l) w i n do w 3 - d eff ec t : 4 i ndepe nd ent w i n dows e n ab le /disa ble co n t r ol w i n d o w b o r d e r color : 16 co lors w i n do w b or de r widt h : p r og ra mma ble formatted: bullets and numbering formatted: bullets and numbering formatted: bullets and numbering formatted: bullets and numbering formatted: bullets and numbering formatted: bullets and numbering
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 18 r ev. a 0 2 /05 /20 08 TW8817 ba si c register setti ng f l ow for buil t-i n o s d contro ller step_1: o s d_window_c o nfigurat i on setting 1. o s d w i n d o w s e le c t 0x0 9 e , b i t1-0 2. o s d w i ndo w d i s able 0x0 9 f, bit 0 3. o s d w i n d o w zo o m multip lie r 0x0 a 9 , b i t7-6 : v, b i t5 -4:h 4. o s d w i n d o w b a ck gro un d b co lo r 0x0 9f, bit 6-4 5. o s d w i n d o w b a ck gro u n d g co lor 0x0 9 f, bit 6 -4 6. o s d w i n d o w b a ck gro un d r color 0x0 9f, bit 6-4 7. o s d w i n d o w b a ck gro u n d c o lor e x t ension 0x0 9 f, bit 7 8 . o s d w i n d o w 3-d e ffec t t op/ bo tt om mode s e lect 0x0 9 f, bit 3 9. o s d w i n d o w 3 - d ef fect l e ve l se lect 0x0 9 f, bit 1 1 0 . o s d windo w 3-d e ffect e n ab le /dis able 0x0 9 f, bit 2 1 1 . o s d windo w h- sta r t loca t ion (see de t a ils in ne xt p a g e ) 0x0 a 1 , b i t0-7 0 x 0a 0, bit 2 - 0 1 2 . o s d windo w v- sta r t l o ca tion (see de tails in ne xt p a g e ) 0x0 a 2 , b i t0-7 0 x 0a 0, bit 5 - 4 13. o s d w i n d o w w i dt h 0 x 0a 3, bit 0 - 5 14. o s d w i n d o w hei ght 0 x 0a 4, bit 0 - 5 1 5 . o s d windo w bo rder _line w i d t h 0x0 a 5 , b i t0-3 1 6 . o s d windo w bo rder _line b c o lo r 0x0 a 5 , b i t4-6 1 7 . o s d windo w bo rder _line g color 0x0 a 5 , b i t4-6 1 8 . o s d windo w bo rder _line r co lo r 0x0 a 5 , b i t4-6 1 9 . o s d windo w bo rder _line e n a b le 0x0 a 5 , b i t7 2 0 . o s d wind ow bo rder co lor e x te nsio n 0x0 a 6 , b i t7 2 1 . o s d wind ow sh a dow w i dt h 0x0 a b , b i t0-3 2 2 . o s d wind ow sh a dow b c o lor 0x0 a b , b i t4-6 2 3 . o s d wind ow sh a dow g co lor 0x0 a b , b i t4-6 2 4 . o s d wind ow sh a dow r co lo r 0x0 a b , b i t4-6 2 5 . o s d wind ow sh a dow e n able 0x0 a b , b i t7 2 6 . o s d wind ow sh a dow c o lor exte nsio n 0x0 a d , b i t7 27. o s d w i n d ow h-s pa c e wi dt h (b et w een b o rde r _l in e an d ch a r a c t er s ) 0 x 0a 6, bit 0 - 6 28. o s d w i n d o w v - s p a c e wi d t h (b et w een b o rde r _l in e an d ch a r a c te rs) 0 x 0a 7, bit 0 - 6 2 9 . character h-space width (between character and character) 0x0a8, bit0-3 0x0ae, bit2 3 0 . ch aracter v- s p ace w i dth ( b e twe en ch aract e r and char acter) 0x0 a 8 , b i t4-7 0x0 a e , b i t3 31. o s d w i n d o w a l pha b l e ndi ng co lo r s e le ct 0 x 09e , bit 4 - 7 32. o s d w i n do w a l pha b l e ndi ng v alu e cont ro l 0 x 0a c, bit 0 - 3 3 3 . window content start address 0x096 3 4 . repeat 1 ? 32 step _2: o s d_ co lo r_ a t t r ibut e / fo nt se tting (o s d ra m ) 1. e n a b le os d ram a c c e ss - 0x 0 94 (b it 0 = 0) 2. o s d ra m add r e s s - 0x 095, 0x 09 6 - t he first ad d r e ss is s tep _1_33 w i n d o w c o n ten t star t a ddress . 3 . o s d r a m d a t a p o rt h i gh ( fo nt a d d r ess ) - 0x09 7 da ta is writ te n to a b o v e addr ess au to m a tica ll y . - 0x09 4_[ 7] = 0 or 0x09 7=8?h f f : fo nt _r o m h 0 0 t o hc9 (20 2 char acters ) - 0 x 0 9 4 _ [ 7 ] = 1 o r 0 x 0 9 7 = 8 ? hfe : fon t _ r am h00 t o h 4 a (m ax 7 5 ch a r a c te rs)
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 19 r ev. a 0 2 /05 /20 08 4 . o s d r a m d a t a p o rt bit 17( i t a l ic eff e ct ), b i t1 8( und e r l i ne eff e ct ) - 0x0 94 bit 6 , b i t5 , b i t4 d a t a is wr itten t o ab o v e a d d r es s au tom aticall y . 5. os d ra m dat a po r t lo w ( c o l o r a t t r i b u t e ) - 0x0 98 d ata is writt e n to ab ove add ress a u t o ma t ica l l y . 6 .re pe at 2) , 3) , 4) , 5 ) - t h e add ress shou ld b e in crea se d b y on e ea ch. s te p _3: co lo r lo o k -u p t abl e se tt ing 1 . se lect c o lor lo ok-up t able wr it e a d d r ess - 0x0 9 c (bit[ 3 : 0 ] ) - b i t[ 3: 0] : th es e 4 b i ts s pe c if y one o f t he 16 e nt r ie s in t h e lo ok-up ta ble . each en tr y is in dexe d t o a dif f e r en t c o lor by it s c o nte nt . - t here ar e 25 6 co lor s a v a i la ble ; b u t o n l y sixtee n o f th em a r e acc ess ib le b y o s d cont ro ller a t a give n time . bit[3:0] default value 0000 00h (000,000,00) 0001 03h (000,000,11) 0010 1ch (000,111,00) 0011 1fh (000,111,11) 0100 e0h (111,000,00) 0101 e3h (111,000,11) 0110 fch (111,111,00) 0111 ffh (111,111,11) 1000 49h (010,010,01) 1001 02h (000,000,10) 1010 10h (000,100,00) 1011 12h (000,100,10) 1100 80h (100,000,00) 1101 82h (100,000,10) 1110 90h (100,100,00) 1111 92h (100,100,10) 2 . color lo ok-u p t a b l e con t ro l b i ts se tting - 0x0 9 d - th e d at a of t he l oo k -up tabl e i s a c ce s s ed t h r o ug h 0x 09 d. - a n in dex 0 x 09d r eg i st er wr ite s t r obes the d a ta int o the co rr esp on d i ng e ntr y p o i n ted b y 0 x 0 9 c [ 3 :0 ]. - co n t r o l bit [ 7:5 ] t hese bits ass i gn ed f o r r co lo r(s e lec t on e o f 8 r color in ten sities). - co n t r o l bit [ 4:2 ] t hese bits ass i g n ed f o r g co lor(se l e c t o ne of 8 g colo r in ten sit i es) . - co n t r o l bit [ 1:0 ] th e s e b i t s a s si g n e d fo r b co lo r(se l e c t one of 4 b col o r in te n s it ie s). r color table bit[7:5] table setting value g color table bit[4:2] table setting value b color table bit[1:0] table setting value 000 8?d0 000 8?d0 00 8?d0 001 8?d32 001 8?d32 01 8?d64 010 8?d64 010 8?d64 10 8?d128 011 8?d96 011 8?d96 11 8?d255 100 8?d128 100 8?d128 101 8?d160 101 8?d160 110 8?d192 110 8?d192 111 8?d255 111 8?d255 3 . repe a t 1) ,2) to pr ogra m ea ch en tr y o f th e look -up t ab l e .
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 20 r ev. a 0 2 /05 /20 08 st ep_ 4 : fon t _ r am _da t a se tt i ng (font ram ) 1 . en ab le font r a m access - 0x0 9 4 (b it 0 = 1 ) 2 . pr ogra m m able s r am address s t a r t p o s i tio n s et tin g for mu lt i-co lo r fo n t. - 0 x 09 b 3 . fo nt r a m a ddr ess s e t t in g - 8 b i t s ( h00 ? h4 a) - 0x0 9 9 - h0 0~ h4a : sin g l e f on t ram( 7 5 prog ra mma ble c haracte rs) - h0 0~ h4a : m u lti-co lor fo nt r a m(25 p r ogr ammab l e cha r a c ter s) ex) 0 x 09 b == h2d se tt ing c a se h0 0 ~ h2c : sin g l e f o n t ra m( 45 p r ogramm able chara c ters) h2d ~ h 4 a : m u lt i-co lor fo n t r a m ( 10 pr ogra m m able char acters) h 2 d (r-co l o r ) , h 2 e ( g - color) , h 2 f(b-co lo r) are on e s e t for 1 mu lti-co lor fon t. 4. f o n t ra m dat a po r t - 0 x 09 a d a t a is wr it ten t o a bove ad dress au to mat i ca lly . 5. re p eat (4 ) at 27 t i m e s f o r on e fon t ram dat a - t h e int e rna l ad dress a u t o ma ticall y in c r e a ses b y o n e each . 6. ne w font ra m a d d r e s s se tt ing ? 8 bit s 7 . repe a t 3) ,4) ,5) - th e font ram a dd r e s s sh oul d b e in c r ea se d b y one ea ch. n ote ) a s for the fo nt r a m con f igur a t io n a n d fo n t bit mapp ing , se e the d e t a i le d descr ipt i o n st ep_ 5 : end of o s d s e tt in g an d e n abl e osd 1. dis abl e o s d ram / font ram a cce ss - 0x 09 4 (bit 0 = 0 ) 2 . o s d w i n dow e n ab le - 0 x 09 e b i t[1 :0] win d ow se le ct 000 : wi n dow 1, 00 1: w i n d ow 2, 010: w i n dow 3, 01 1: win d ow 4 - b i t0 = 1 o f 0 x 09 f
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 21 r ev. a 0 2 /05 /20 08 o s d w i ndow start lo cati o n : bui l t - i n o s d c ontro ll er o s d windo w h _sta r t lo ca tion (n): 0 x 09 e bit[ 1: 0] win d o w select , 0x0 a 2, 0a 0 increm ent b y 1 a t a t i me n = 0, 1 , 2 , 3? p i xe l 1 whe n n = 0, 1 n o s d_w i nd o w st a r t_ p i x e l 1 p i xe l 1 (b eg in with pixe l 1 ) 2 p i xe l 2 3 p i xe l 3 n pixel n o s d windo w v _ st a r t loca tion ( m ) : 0 x 09 e b i t[1 :0 ] wind ow se lect, 0 x 0a2 , 0 a 1 increme n t b y 1 at a tim e m = 0 , 1, 2 , 3. . . . l i ne 1 whe n m = 0 ,1 m osd _ win dow s t art _ l in e 1 lin e 1 (be g in wit h line 1) 2 lin e 2 3 lin e 3 m line m 0 1 2 0 19 ad dr e s s t h e ch arac ters can b e d i sp la y e d o n th e scr een in fo ur user d e f in ed win d o w lo ca tions o f a n y s i ze fro m 1 to 25 6 c haract e rs . t here is a limit o f 2 5 6 ch arac ters t h a t m a y be d i s p la y e d o n scr een a t o n e tim e in a ll win dows c o m b ined. ex amp l e w i nd ow #1 : a ddr ess 0 ? 2 (3 c harac ters) w i nd ow #2 : a ddr ess 3 ? 10 0 ( 98 ch ar acters) w i nd ow #3 : a ddr ess 10 1? 2 54 (1 54 ch a r a c te rs) w i n d o w # 4 : a d d r ess 25 5 ( 1 char acter) o s d_ r a m confi g u r a t i on 253 254 255
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 22 r ev. a 0 2 /05 /20 08 fon t ram a d dr es s 8-b i ts inter nal char act er ad dr e s s 5- b i t s aut o mati ca l l y in creas e s f ont ra m a d d r e ss shoul d be incr eas e d by ea c h f ont dat a . (0 ~ 74) internal character address automatically increases by font data write sequence. (0 ~ 26) f on t ra m a dd r e ss 7- bits 7 6 5 4 3 2 1 0 4 3 2 1 0 line 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 1 6 17 19 20 21 2 2 23 24 25 26 4 pixels 12 pixels f o n t b i t ma p 12 x 18 do ts = 1 c h a racter b i t 3 b i t 2 b i t 1 bi t 0 bi t 7 bi t 6 b i t 5 b i t 4 font ram (2048 x 8 bits) 765 4321 0 a d dr es s 0 1 s i n g le c o lo r fo nt o r m u l t i-c o lo r f on t 3 a d d r ess ar e o ne m u lti - c o l o r f ont 72 73 74 19 0 8 7 f o n t _ad dress (12-bits) bit 19: r e se rv ed bit 18: u n d e r line eff ect on bit 17: i t alic e ffect o n bit 16: f o n t _ r am on bit 15 - 8 : fon t ad d r ess at tr ib ut e (8 -b its) bi t 7: c har act e r ? s co l or exte nsio n bi t 6: c har act e r ' s back g r o u n d r bi t 5: c har act e r ' s back g r o u n d g bi t 4: c har act e r ' s back g r o u n d b bi t 3: b l i n k on bi t 2: c har act e r r bi t 1: c har act e r g bi t 0: c har act e r b 18
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 23 r ev. a 0 2 /05 /20 08 TW8817 al pha ble nd i ng for o s d w in dow t h e t w881 7 u s es " a lp ha ble n d i ng" in o s d 4 se pa rat i on w i ndo w s & 16 s e p a r a tio n col o rs. al ph a ble n d i n g mix e s ( adds) the v i deo s i g nal a nd o s d sign al at t h e fo llowin g s pecif ied lev e ls. in o the r wo rd s , a l p ha b l e nding de ter mine s th e t r an sp are n c y o f th e o s d windo w e a ch colo r t o in r e la tion t o v i de o s i gna l. w h e n alph a blen d i n g is disa bled, o n l y o s d dat a i s di sp lay ed i n o s d w i nd ow . th e alp ha ble nd i ng l e vel se le ct i on are 4 - b i t as si gn e d, it can su pp ort 8 d i ff er ent l e vel con t r ol. t he al p ha bl endi n g l e v el b i t s an d al pha b l en d i n g co l o r s electi on bi ts a r e i n r e g i ster 0 x 0 9 e, 0x 0 a c f or eac h w in d ows( w i n dow co n t ro l b y reg i s t e r 0x9e b i t [ 1: 0]). al pha [3: 0 ] vi de o le v e l 00 00 0.00 % 00 01 1 2.5 00 10 2 5.0 00 11 3 7.5 01 00 5 0.0 01 01 6 2.5 01 10 7 5.0 01 11 8 7.5 10 00 100 al pha b l endi ng c onc ept : x + video le osd dat a v i de o d at a x 1 ? video level
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 24 r ev. a 0 2 /05 /20 08 m i croc ontro ller interface t h e t w 8 817 r e g i s ters are a c cesse d v i a 2- wire ser i a l bus int e rf ace . it o p e rat e s as a slav e d e vice . se ria l clock a nd da ta lin es t r a n sfe r d a t a f r om t h e bus mas t e r a t a ra te up to 400 kb /s. bu ilt -in m i cro contro lle r tw 8 8 17 ha s bu ilt -in m i cr o c on t r oll e r w h ich s u p p o r t s s e ve ral inte rface . ? su pp ort e x t ern a l s p i in ter f a ce . ? su pp ort i2c ma st e r in ter face with g p i o { po rt 1.0 s c l , p o r t 1 .1 sd a}. ? su pp ort u p t o 8 m c u g p io { p o r t 2. 0 g p 0 ~ por t 2 .7 g p 7} . ? su pp ort u a rt int e rface wit h g p i o { p o rt 3 . 0 r x d, p o r t 3. 1 t x d} . ? su pp ort ir or in ter ru p t with g p io { por t 3 . 2 ir}. power manag ement t he t w88 17 s uppor ts panel p o w e r seq uen cing . t y p i ca l t f t pane ls re qu ire d i ff erent p a r ts o f th e p an e l p o w er to be ap p l ie d in the r i g ht sequ ence to a v o i d pr e m a tur e dam age to th e p a ne l . p i ns a r e p r ov id e d to con t ro l t h e p a n e l ba ckligh t gen er ato r, d i gita l c i rcu i t r y an d p a n e l driver, s e p a ra te l y . t h e t w 88 17 c o n t ro ls th e po we r up and po we r d own s equ en ce fo r the lcd pa n e ls . t he time lap s es b e t w e en d i f feren t sta g es of th e s eque nc e a r e ind ep enden tl y p r ogra mma ble to mee t va r i o us po we r seq ue ncin g r equ ir emen ts . t h e t w8817 a l so su pp orts ve sa tm dp m s f o r m o ni to r p o w e r ma n a gem ent . it ca n d e te ct t h e dp m s st a t u s from in pu t s y n c s i gna ls an d au to ma tica ll y cha n g e in t o o n/o f f m ode . to s uppor t th e p o w er ma na ge m e n t, th e t w88 17 has t h re e o pera ting mod es: p owe r o n mod e , p o wer o f f m ode , and pa ne l o f f mode. a ll the dpms pow er s a vi ng mode w ill be cover e d b y the pow e r o f f mode.
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 25 r ev. a 0 2 /05 /20 08 clo s ed capt ion ing a nd exten ded data ser v ice s cl os ed ca pt io n (cc) ve rt i c a l blan k i n g int e r val sca n lin es ar e on th e odd fie l d nt s c line 2 1 . exte n d ed d ata ser v ices ( e d s ) s c a n lin es ar e o n t h e even fie l d nts c li ne. a cl ose d ca pt io n ( c c) s c a n lin e o n a n nts c -b a s e d sy st em is m a d e of 25 bit pe rio d s at a 0. 5 03mhz ra te . t he d at a is an a na l og s i g nal be g i nn ing w i t h a pac ket h e a d e r. it co nt ain s a clo ck sy nchro n i zat i on cod e con s isti ng of 14 b i t s of do ub le -f re qu en c y ru n-in cl ock at 1. 00 6 m h z, a 2 - bit f r a m in g c o d e . th e d a t a of 1 6 bit s / 2 by tes f o llow s t h e p a cke t he ad er. e a ch o f thes e 2 b y t e s is a 7 bit + o d d parity a s c i i ch ar a c ter wh ich repr ese n t s te xt or con t ro l c h a r act e rs for po sit i o ni ng o r d i spl ay cont ro l . for t he pu rp os e s of cc o r eds , o nly t he y com p on en t o f th e vi de o si gn al i s u s e d . t h e r ef ore , the in put co mposit e v i d e o ha s to go thr ou g h the y / c sep a rat i on t o e x t r ac t y c o mp onent fo r furt her decod in g . t he tw 88 17 can be pr og ra mmed to d e c od e cc or ed s da ta b y s e tting r egis ter 0 x 1 b . sinc e t h e c c a nd ed s are in depe nd en t, t he r e cou l d b e on e o r bo t h in a pa rt icu l ar fram e. a t y pic al wa ve for m is sh o w n in f i g u re 5. in th e cc/ eds d e cod e mo d e , the d e co de r m o nitor s t h e a pprop r i a t e scan lines lookin g f o r the clock run - in and start bit s pattern. it found , it locks to the cl ock r u n- i n , the c aption data is s a mpl e d and loaded i n to s h ift r e g i s ters, an d t h e d ata is th en tra n sferr ed to t h e ca pt io n d a t a f i fo . t he t w88 17 pr o v id es a 1 6 x 10 loca tion fifo f o r s toring cc/e d s da ta . on ce the vid eo d e co de r det ect s the s tart sig n a l in the cc /eds signal, it captur es th e low b y te of cc/e d s data fir s t and checks to see if the fi fo i s f u ll. if the f i fo is not fu ll, t h e n the da ta is s tored in th e f i fo , a n d is av a i lable to t h e us e r th rough th e cc_dat a regis t er (0 x1a) . t he h i g h b y t e of cc/ ed s dat a is ca p t u r e d ne xt an d p l aced in the f ifo . upon b e i ng p l aced in the 10 -bit f i f o , two add ition a l bits are a ttach ed t o th e cc/ ed s da t a b y t e b y t w8817 ?s cc/ed s decod er. t h e s e t w o bit s ind i c a te w het he r t h e giv en by te st o r e d in th e fi fo c o rr esp o n d s to cc o r e d s dat a an d w het he r i t is the high or lo w b y t e of cc /e ds . t h es e two b i ts are ava i la ble to t h e us er t h rou gh th e cc_st a t us r e g i s ter bit s cc _ e d s a n d lo _h i, r e spec tiv e l y . a s s t o r ed in t he f i fo , l o _ h i is b i t 8 a nd cc_ eds is b i t 9. a d d i tio n a l l y , t h e t w881 7 s tor es t he results o f t h e p a r i t y c heck in the pa r i t y _e rr bit in t h e cc_ s ta t u s r e g i s ter . th e 1 6-l o c a ti o n fi fo ca n h old ei gh t l i n es wo rt h of cc/ e ds dat a, a t t w o b y t es pe r l i ne . i niti al l y whe n t h e f i f o is emp t y , bit em p t y i n the cc _ s tat u s re g i ste r (0 x1a) is se t low and in d i c ates t hat no d a t a is av ail abl e in the f i fo. subsequentl y , w hen data ha s been stor ed in the f i fo, the empty bit is set to logi cal h i gh. o nc e the f i f o is h alf fu ll, the cc _ val id in terr upt p i n sign a l s to th e s y ste m tha t th e f ifo co n ten t s sho u ld be read in t h e ne ar fu tu r e . t h e cc va lid bit is enab led via a bit in th e cc_ s t at us r e g i s t e r ( 0 x1 a) . t h e sy st e m co n t roller can th e n poll th e cc va lid b i t in th e stat us re giste r ( 0 x00 ) to en su re t hat it was t h e tw8 8 1 7 t hat in itiate d t he ccv a l id int e rru pt . fi gu r e 5 ty p ic a l cc /ed s scan li ne w a v e for m clock run-in frame code
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 26 r ev. a 0 2 /05 /20 08 w h e n t he first b y te o f c c / eds dat a is d e cod e d an d stor ed in t he fifo , t he da ta is imm e d i a t e l y p l a c e d in t he cc_da ta and cc_s t a t us re gi st er s a nd i s a v aila b l e t o be rea d . on ce t h e dat a i s r e a d from t he cc_ d a t a re gi st e r , th e inf o rm at i on in t he n e x t lo ca ti on of t h e fi fo is pla c ed i n t he cc_ d a t a an d cc _s t a t u s reg i s ters. i f th e co n t r o ller in th e s y s t e m ig nores tw 881 7 ? s c c val i d b i t for a s uffic i en tl y long per i od of time, then the cc/e d s f i fo w ill bec ome full and the t w 8817 w ill not be able to w r ite additional dat a to the f i fo . any incomi ng b y tes of data w ill be lost an d an overfl ow condit ion w i ll o ccur; bit overflow in the c c _s t a t u s r e gi s ter w ill be set to a logic a l one. t h e s y s t em ma y c l ear the over fl ow co nd it io n b y rea d in g t he cc /e ds dat a an d cre a t i n g sp a c e i n t h e fi fo f o r new inf o rm at io n. as a res u lt , t h e o v er flo w b i t is reset to a log i ca l zero . t here w ill r o utin e l y b e a s y n chro nous re ads and w r ite s t o th e cc /eds f i fo. the w r it es w ill b e fr om th e cc /ed s cir c uitr y an d t h e rea d s w ill o c c u r a s the s y s t e m con t ro ller re ad s t he cc/ e ds d a t a fro m tw 88 17. t hes e r e ads and w rites w ill s o metimes oc cur si multan eo usly , and the t w 8817 i s de signed to gi v e pri o r i ty to th e re ad o p e r a t io ns . in the c a se whe r e t h e cc _dat a r e g i s ter d a t a is s p ec ific ally b e ing rea d to cle a r an ov e r f l ow c o n d i t io n, t he simu lt an eo us o c c u rre n c e of a r e a d and a w r it e will not c a u s e t h e ov erf l ow bit t o be r e se t, ev en t houg h t h e rea d has p r ior i t y . an ad d i tio n a l rea d must be m ade to th e cc _dat a reg i st er in or der to c l ear the ov erfl ow condition. a s al w a y s , the w r ite data w ill be lost w h ile the f i f o i s i n ov er fl ow condition. tw o wi re seri a l b u s interface th e tw o w i re se ri al b u s i nte rf a c e i s u s ed t o all ow an e x t e r na l mi cro- co nt ro lle r t o w r it e c ont rol d at a to , an d r e a d co n t r o l or o t h e r in for m a tion from th e tw 8 8 17 reg i s ters. scl k is t h e se rial clo c k an d s d at is the d a t a lin e . b o th line s are pulled h i g h b y r e sis tors conne cte d t o v dd. i c s com mun ica t e o n the b u s b y p u l ling sc l k and s d at low t hr o ugh o pe n dr ain ou t p u t s. in n orma l o p e r a tio n th e m a ster g enera tes a l l clock p u lse s , b u t c o n t rol of the sd a t lin e a l terna tes back an d for th b e t wee n th e mast er an d the slave . for f i gure 6 d e fi n i ti on o f t w o- w i re seri a l bus inte r f a ce b u s start and st op sdat start condition stop condition deleted: the fifo is reset when both cc and eds bits are disabled in the cc_status register; any data in the fifo is lost. ?
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 27 r ev. a 0 2 /05 /20 08 b o t h r ead and write , e a ch b y t e is t r ansfer re d msb f i rs t, and t he dat a b i t is v a lid wh ene ve r s c lk is h i gh . t h e t w 8817 is o pera ted a s a bu s slav e d e vice . t h e mo st sign ifica n t 7 - b i t s ar e f i x e d . t h e 7- bit addr ess fie l d is co nca tena te d with t h e r e a d / w rite co ntr ol b i t to form t he f i rs t b y t e tr ans f e rre d d uring a n e w tr ansfer . i f the r ead/w rite c o ntrol bit i s hi gh the next b y te w ill be read fr om the slav e devi c e . if it i s low the n e xt b y te w ill b e a writ e to t h e slave . wh en a bus m a s ter ( the h o s t microp rocessor) drives sda t from high t o low, wh ile sclk is h i g h , th is is def i n ed to b e a st art co nd it io n ( see fig u re 6. ). all sl ave s on th e bu s li st e n t o d e termine wh en a st a r t cond ition ha s b e en a sser ted . after a start condition, all sl av e devic e s liste n for their de v i ce addres s e s. t h e host then sends a b y te cons ist i ng o f t h e 7-b i t s l ave d e vice id an d t h e r / w b i t. t h is is sh o w n in f i gur e 7 . (for t h e t w881 7, the n e x t b y te is no rm all y th e ind e x t o th e tw 8817 reg i ste r s a n d is a writ e to t he tw 88 17 ther efo re t he fir s t r / w b i t is norma ll y lo w.) a fte r tr an s mit t i n g the d e vice a d d r es s and t h e r / w b i t , th e mas ter must r e le ase th e sd a t line wh ile h o l ding s c l k lo w, a n d wa it fo r an ackn owle dg e m e n t fro m t he slave . if th e a ddress m a t c hes the d e vice a ddres s o f a slave , t h e slav e w ill r e sp ond by d r ivin g th e sd at line lo w t o ackn o w le dge th e cond ition . t he mas ter w ill then continue w i th t he nex t 8- bit transfer. if no devi c e on t he bus res p onds, the master tr an sm its a st o p con d ition an d end s t he cy c l e . no tice tha t a succe ssf ul tr ansfer a l way s in clu des nin e c l o c k pul s es. t o write t o the in ter na l re g i ster of t het w8817 , the mas ter send s an o t h e r 8-bit s o f d ata, th e t w881 7 lo a d s this to the regis ter point ed by the internal index r e gi ster . t he t w 88 17 w ill ac k now ledge the 8-bit data tr an sf e r an d a u t o ma tic a ll y in cr e m e n t t h e ind e x in p r ep aratio n fo r the n e xt da t a . t h e m a ste r c a n do m u lt ip le w r ites to the TW8817 if the y ar e i n ascending sequenti al order . after each 8-bit t r ans f e r t he t w 8817 w ill a c kn owle dg e th e re ce ip t o f t h e 8-b i t s wit h a n ack nowle dg e pulse . t o e n d a l l t r a n s fers t o the t w 8 8 1 7 t h e host w ill issue a s t op c o nditi on. fig u re 7 o n e complete serial bus i n terface register w r it e sequence sclk device id (1-7) r/w index (1-8) data (1-8) sdat start condition stop condition a ck a ck
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 28 r ev. a 0 2 /05 /20 08 a t w 88 17 rea d c y c l e h a s t w o ph a s es . th e firs t ph ase is a wr ite to t he in terna l index re g i ster . t he s e con d p hase is the re ad from the da ta re gister . ( s ee f i gur e 8). t h e h o st in it iat e s the first ph ase b y s e nd in g the st art co nd itio n . i t t h e n sends th e s l ave d e vic e id tog e ther with a 0 in th e r/ w b i t po sit i o n . t h e in de x is the n se nt fo l l ow ed by eit her a sto p co n d it io n or a se con d st art co nd it io n. th e se co n d ph as e sta r t s w i t h t h e seco nd sta r t co ndit i on. t h e mast er th en re se nds th e same slave d e vic e id with a 1 in th e r / w b i t pos itio n t o in di cat e a re ad . th e s l a v e w ill t r a n s f e r t h e co nt ent s of t he d es i re d re gi st er. th e m a st er r em a in s i n co nt rol of th e cl ock. a f te r tra n sf er ri ng e i g h t bit s , t he s l ave r e lea s es. t he ma s t e r takes con t ro l o f t he sd a t line and ac k n ow ledges the r e c e ipt of data to the slave. t o ter m i nate the l a s t tr an sfer the master w ill i ssue a ne ga ti v e a ckn ow led g e (sda t is l e ft hig h du rin g a cl ock pul se ) a n d iss ue a st o p co n d it io n. ta b le 2 TW8817 seri a l bu s in t e rface 7-bi t sla v e ad dress and rea d w r ite b i t serial bus interface 7-bit slave address read/write bit 1 0 0 0 1 0 1 1= read 0=write figure 8 one complete serial bus interface register read sequence re-start condition sclk device id (1-7) r/w index (1-8) sdat a ck data (1-8) stop condition nack start condition device id (1-7) r/w a ck
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 29 r ev. a 0 2 /05 /20 08 t h e t w 8 8 1 7 con t a i ns more th an 256 inde x reg i st ers . s i nce the ind e x d a t a f o r s e ria l bu s access is on l y e i ght b i ts wid e , a p a ge mechan is m is used t o access the se reg i s t e r s. t he b i t 0 of in de x 0 x ff is u s ed to se le ct eit h er t he f i rst pa ge of 255 re gi ste r s or th e se c o nd p ag e o f 25 5 re gi ste r s. i n t he re gi ste r m ap, t h e in dex co nsis t s o f 9 bit s . t h e m s b den o tes t h e co nte n t of bit 0 of ind e x 0 x ff , a nd the res t 8 b i t s corr esp o n d to t h e se ria l bus ind e x da ta . h e nce 0 x 000 de no tes the in de x 0 of p a g e 0, wh ile 0 x 1 0 0 de n o te s th e in d e x 0 of p a ge 1. in dex 0x ff is sh are d b e t w e en pa ge 0 an d pa g e 1 . test modes the te s t 1 inp u t p i n pr ov ide s tes t m o de s elec tion . i f th is pin is lo w a t th e r i s i n g edge o f th e r eset # p i n a nd re m a ins lo w, t h e t w8 817 is in its norm a l o p e r a t ing mo de . t a b l e 3 sho w s t he oth er t e st m odes ma d e av ail abl e w i t h this pin. ta bl e 3 tes t m o de s test mode test1 bef o r e reset# rising edge test1 after reset# rising edge descr i p t i o n n or m al 0 0 n or mal operation ou t p u t tri -st a te 0 1 in t his mode, all pin output drivers are tri-stated. pin leakage current parameters can be measured. ou t p u t s h i gh 1 0 in t h is m ode, a l l p i n o u t pu t d r iv e r s a r e f o r c e d t o t h e h i gh o u t pu t s t a t e . v oh and i oh can be measured. ou t p u t s l o w 1 1 in t h is m ode, a l l p i n o u t pu t d r iv e r s a r e f o r c e d t o t h e l o w ou tpu t s t a t e . v ol and i ol can be measured.
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 30 r ev. a 0 2 /05 /20 08 TW8817 package pin diagram TW8817 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p w rdn vs s3 3_3 vdd33_ 3 te s t1 rst b xt i xt o p3.2 (in t 0) p2.0 /p w m 2 fpb 5 fpb 4 fpb 3 fpb 2 fpb 1 fpb0 fpg5 fpg4 fpg3 fpg2 vss33_2 a vs3 a dcin0 a dcin1 sense1 sense0 a vd3 p2.3 p2.2 p2.1 spi_clko spi_di spi_do spi_csn vss18_3 vdd18_3 p3.1 (txd) p3.0 (rxd) p1.0/scl p1.1/sda mcuen av d 1 yi n 1 yi n 0 yg n d yo ut av s1 ci n av d 2 av s2 f p bi a s / ccfl p / l ed_ou t fp p w m1/ccfl n vdd18_ 1 vs s1 8_1 tc l r l/gpo 0 fp p w c trcl k t rud l/gp o 1 t c i n v/t c rev/ gp o2 p o l_ a/ c s yn c / g p o 3 pol_b/pll_c k/gpo4 tclp fpclk/del_c k vdd33_1 vss33_1 trspt/fpvs/del_vs tcspl/fphs/del_hs troe/fpde(fpbias) tcspr/gpo5 trspb/gpo6 fpr0/del0 fpr1/del1 fpr2/del2 fpr3/del3 vdd18_2 vss18_2 fpr4/del4 fpr5/del5 fpg0/del6 fpg1/del7 vdd33_2
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 31 r ev. a 0 2 /05 /20 08 pin description t his sec tio n prov id es a d e t a iled d esc rip tio n o f eac h pin f o r the t w8817 . the p i ns are a r ra ng ed in fu nction al g r oups a c co rding t o t h e i r ass o cia ted in t e r face . t h e a c ti ve s tate of t h e si g nal is de termined b y th e t r a iling s y m b ol a t th e e nd o f th e si g nal n a me . a "#" s y m b ol in dica tes t h a t the s i gnal is active o r assert ed at a low vo lta g e lev e l. w hen " # " is n o t presen t afte r t h e s i g nal n a me , t he sign a l is a c t i ve at the h i g h v o lta ge leve l. th e pin de sc ri pt io n al so in cl ud es t he b u ff e r di re ct i on an d ty pe use d fo r th at pi n. p i n # i/o n a me d escr iption r ecom m ended connection of unused pins analog i /f sig n als 1 p av d1 analo g v dd +1 .8 v 2 a y i n1 analo g comp o s i t e or l uma i nput 1 connect to analog ground 3 a y i n0 analo g comp o s i t e or l uma i nput 0 connect to analog ground 4 p y g nd y in p u t g r ou nd 5 a y o u t y output ( y o u t or y + c o u t ) open / unconnected 6 p av s1 analo g gr ou nd 7 a c i n analo g comp on ent c i nput connect to analog ground 8 p av d2 analo g v dd +1 .8 v 9 p avs2 analo g gr ou nd 7 5 p av d3 analo g v dd +3 .3 v 7 6 a sense0 analog sensing 0 input 7 7 a sense1 analog sensing 1 input conn e c t to anal og gro un d 7 8 a adcin1 l o w speed ad c in put 1 7 9 a adcin0 l o w speed ad c in put 0 8 0 p avs3 analo g gr ou nd d i git al i / f sign als o fpbias po w er on/ o f f contr o l for pa nel backli ght bi a s o ccf lp ccf l dr ive r po lar i ty ( p o s i t i v e ) 10 o le d _ o u t mcu le d o fpp w m1 p w m con t r o l for p anel backli ght 11 o cclf n ccf l dr ive r po lar i ty ( n ega tiv e ) 1 2 p vdd1 8 di g i tal c o r e p o w e r +1 .8v 1 3 p vss18 di g it a l c o r e gr ou n d o tclr l tcon left ri ght s el e cti o n ( left: h i gh , ri ght: low ) 14 o gpo 0 gen e r a l p u r pose o u tput 1 5 o fpp w c po w er on/ o f f contr o l for fl at p an e l dis pla y 1 6 o t rclk t c on r o w dr i ve r sh i ft clock
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 32 r ev. a 0 2 /05 /20 08 o tru d l tcon u p d own s e l ecti on (up : hi gh, do w n : l o w ) 17 o gpo 1 gen e r a l p u r pose o u tput o tcinv tcon c o l u m n dr ive r inv e r si o n o tc re v tc on c o l u m n d r ive r inv e r s i o n 18 o gpo 2 gen e r a l p u r pose o u tput o pol_a tcon column driver polarity a o csy nc vid e o csy nc signal outp u t 19 o gpo 3 gen e r a l p u r pose o u tput o pol_b tcon column driver polarity b o pll_ ck pll cl o ck o u t put 20 o gpo 4 gen e r a l p u r pose o u tput 21 o tclp tcon column driver load pulse o fpcl k 1 fl at pa nel clo ck o u t put 22 o del_ck delt a r g b cl oc k 2 3 p vdd3 3 di g i tal i/o pow e r +3.3v 2 4 p vss33 di g it al i / o g r ou nd o t rspt t con r o w dr ive r sta r t i ng pulse ( t op s t ar t ) o f p vs v e r t i c al s y n c o u t p ut f o r f l at pa n e l 25 o del_vs delt a r g b vsy n c o tcspl t c on col u mn dr iv e r s t a r t p u l s e ( lef t t o ri g ht sc an) o fphs hori zont al sy nc out put f or fl a t p anel 26 o del_hs delta r gb hsy n c o troe tcon row driver output enable 27 o fpde dat a vali d f or flat pan e l o tcspr tcon column driver start pulse (right to left scan) 28 o gpo 5 gen e r a l p u r pose o u tput o trs p b row driver st ar tin g p u ls e (b ot to m st a r t) 29 o gpo 6 gen e r a l p u r pose o u tpu t i/o fpr0 red flat panel output bit [0] 30 i/o del0 delt a r g b out put [0] i/o fpr1 red flat panel output bit [1] 31 i/o del1 delt a r g b out put [1] i/o fpr2 red flat panel output bit [2] 32 i/o del2 delt a r g b out put [2] i/o fpr3 red flat panel output bit [3] 33 i/o del3 delt a r g b out put [3] 3 4 p vdd1 8 di g i tal c o r e p o w e r +1 .8v 3 5 p vss18 di g it a l c o r e gr ou n d i/o fpr4 red flat panel output bit [4] 36 i/o del4 delt a r g b out put [4] i/o fpr5 red flat panel output bit [5] 37 i/o del5 delt a r g b out put [5] i/o fpg0 green flat panel output bit [0] 38 i/o del6 delt a r g b out put [6]
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 33 r ev. a 0 2 /05 /20 08 i / o f p g 1 green flat panel output bit [1] 39 i/o del7 delt a rgb o u t put [7] 4 0 p vdd3 3 di g i tal i/o pow e r +3.3v 4 1 p vss33 di g it al i / o g r ou nd 42 i / o f p g 2 green flat panel output bit [2] 43 i / o f p g 3 green flat panel output bit [3] 44 i / o f p g 4 green flat panel output bit [4] 45 i / o f p g 5 green flat panel output bit [5] 4 6 i/o fp b 0 b l u e fla t p a n e l outp ut b i t [ 0 ] 47 i / o f pb1 bl ue f l at pa ne l o u t p u t b i t [1 ] 4 8 i/o fp b 2 b l u e fla t p a n e l outp ut b i t [ 2 ] 4 9 i/o fp b 3 b l u e fla t p a n e l outp ut b i t [ 3 ] 5 0 i/o fp b 4 b l u e fla t p a n e l outp ut b i t [ 4 ] 5 1 i/o fp b 5 b l u e fla t p a n e l outp ut b i t [ 5 ] i / o p2 .0 m cu port 2. 0 52 i / o pw m 2 pw m v o lu m e co n t r o l 5 3 i/o p3 . 2 ( i n t 0) m cu po rt 3. 2 ( m cu int 0 ) 5 4 o x t o cry s tal t er min a l ( i f cry s ta l i s us ed) 5 5 i x t i crystal terminal (if crystal is used) or oscillator input 5 6 i rs t b res e t p i n 5 7 i test 1 pro ducti on te st pin connect to vss33 5 8 p vdd3 3 di g i tal i/o pow e r +3.3v 5 9 p vss33 di g it al i / o g r ou nd 6 0 i p w rdn p o we r d o wn p i n conn e c t to vs s3 3 6 1 i mcue n mcu ena b l e i/o p1 . 1 mcu por t 1 . 1 w hen m cuen = 1 62 i/o sda 2-w ir e i2c i n t e r f a c e d a t a pi n wh en m cuen = 0 i/o p1 . 0 mcu por t 1 . 0 w hen m cuen = 1 63 i/o scl 2-w i r e i2c i n t e r f a c e c l o ck p i n w hen m cuen = 0 6 4 i/o p3 .0( rxd) mcu port 3 . 0 (m cu rxd ) 6 5 i/o p3 .1( t xd) mcu port 3 . 1 (m cu t x d) 6 6 p vdd1 8 di g i tal c o r e p o w e r +1 .8v 6 7 p vss18 di g it al c o d e gr ound 6 8 o spi_csn spi csn ( l ow enabl e ) 6 9 o s p i_d o s p i d ata out 7 0 i s p i_d i s p i d a ta in 7 1 o s p i_c l k o s p i cl ock out 72 i / o p2 .1 m cu port 2. 1 73 i / o p2 .2 m cu port 2. 2 74 i / o p2 .3 m cu port 2. 3
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 34 r ev. a 0 2 /05 /20 08 parametric information a c / dc el ectrical param e t e rs tab l e 4. a bso lut e maxi mum r a tings p a ra me ter s y m bol min t y p ma x units av d 1 , a v d 2 (m eas u r e d t o av s1, av s2) v dd am - - 1 .92 v av d 3 ( mea s u re d to avs3) v d d a 33m - - 3.6 v v dd1 8 ( m e a s ured t o vs s1 8) v dd m - - 1 .98 v v dd3 3 ( m e a s ured t o vs s3 3) v dd em - - 3.6 v volta ge o n an y d igi ta l sign al p in (see th e no te below) - vs s3 3 ? 0. 5 - 5. 5 v ana l o g inp ut vo ltag e ( s up pli e d b y 1.8v) - av ss ? 0. 5 - 1 . 92 v ana l o g inp ut vo ltag e ( s up pli e d b y 3.3v) - av ss 33 ? 0.5 - 3. 6 v stor ag e t e mpe r atu r e t s ?6 5 - +1 5 0 c j u nc t io n t em p er at u r e t j - - +125 c vap or ph as e sol der i n g( 1 5 second s ) t vsol - - +220 c not e : st res s e s a bo v e t ho s e list ed may ca u s e pe rm a ne nt da m a ge to t he d e v i c e . thi s i s a st re ss r atin g o n l y , and fu nction a l o pera t ion a t t h e s e o r an y ot h e r con d ition s abov e those lis t e d in th e o p er at io nal sect ion of th is sp ecificatio n is not im plied. e x pos ure to abs o l u te max i mum rating c o nditions for exten d ed per iods may affect devi c e reliability . th i s d e v i c e e m p l oy s high -i m pe da n c e cm o s de vi c es on all si gna l p i ns . i t m u s t be han dled a s an e s d-sen s itive dev ice . v o lt a g e on an y s i gna l p i n t h at e x ce ed s th e ran g e s list in t a b l e 4 ca n in duce d e st ruc t iv e la tch-u p . ta bl e 5. cha r ac te ris t i cs p a ra me ter s y m bol min t y p max un its su pp l y power supply ? io v dde 3.15 3.3 3.6 v power supply ? analog 3.3v v dda33 3.15 3.3 3.6 v power supply ? analog 1.8v v dda 1.62 1.8 1.92 v power supply ? digital v dd 1.62 1.8 1.98 v ambient operating temperature t a -40 +85 c analog supply current (cvbs only) iaa - 40.54 - ma digital i/o supply current * idde - 17 - ma digital core supply current * idd - 63 - ma * not e: di gi t al i / o an d c or e s u ppl y c ur r e nt m e a s ur e m e nt i s b as e o n w v ga i np ut ( 40m hz cl oc k r a t e) w i t h sm pte p at t e r n. digital inputs input high voltage (ttl) v ih 2.0 - - v input low voltage (ttl) v il - - 0.8 v in put h i gh vol t ag e ( x ti) v ih 2.0 - v d d 33 + 0. 5 v input low voltage (xti) v il - - 0.8 v input high current (v in =v dd ) i ih - - 10 a input low current (v in =vss) i il - - ?10 a input capacitance (f=1 mhz, v in =2.4 v) c in - 5 - pf
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 35 r ev. a 0 2 /05 /20 08 parameter symbol min typ max units dig i tal o u tput s output high voltage (i oh = ?4ma) v oh 2.4 - v dd33 v output low voltage (i ol = 4ma) v ol - 0.2 0.4 v 3-state current i oz - - 10 a output capacitance c o - 5 - pf an alog in pu t analog pin input voltage vi - 1 - vpp y i n0, y i n 1 , y i n 2 a nd y i n 3 in put r a ng e ( a c c o upl ing requ ired) 0.5 1. 0 2. 0 vp p ci n0 , c i n1 , c i n2 amp l i t u d e r a n g e ( a c c o up lin g re q u ired ) 0.5 1. 0 2. 0 vp p vi n 0 , v i n 1 a m pl i t ud e r a ng e (a c c o u p l i ng r equ ir e d ) 0.5 1. 0 2. 0 vp p se n 0 , s e n 1 d c i n pu t r a ng e 0 . 65 1. 65 2. 6 5 v analog pin input capacitance c a - 7 - pf an alog outp ut c o m_ out(i = 20 0 u a max ) d c ou tpu t 0.6 5 - 2 . 65 v a dcs adc resolution adcr - 9 - bits adc integral non-linearity ainl - 1 - lsb adc differential non-linearity adnl - 1 - lsb adc clock rate f adc - 27 60 mhz video bandwidth (-3db) bw - 10 - mhz h o r i z o ntal pl l line frequency (50hz) f ln - 15.625 - khz line frequency (60hz) f ln - 15.734 - khz static deviation f h - - 6.2 % su bc a r r i er pl l subcarrier frequency (ntsc-m) f sc - 3579545 - hz subcarrier frequency (pal-bdghi) f sc - 4433619 - hz subcarrier frequency (pal-m) f sc - 3575612 - hz subcarrier frequency (pal-n) f sc - 3582056 - hz lock in range f h 450 - - hz cry s ta l sp e c n ominal freq uen c y ( f u nd amenta l ) - 27 - mh z de v i at i o n - - 50 pp m temperature range ta 0 - 70 o c load capacitance cl - 20 - pf series resistor rs - 80 - ohm
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 36 r ev. a 0 2 /05 /20 08 80 -p i n tqfp pack age mecha n i cal draw i n g r2 r1 s l 3 2 ga g e plane 0.25mm 1 e e1 e2 d d1 d2 TW8817 top b e a 1 a a 2 l1 l c
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 37 r ev. a 0 2 /05 /20 08 mil lim eter inch sy m bol min . n o m. max. min. nom. max. a -- - -- - 1.20 --- --- 0.047 a1 0. 05 -- - 0. 15 0. 00 2 --- 0.006 a2 0. 95 1. 00 1. 05 0. 03 7 0 .0 3 9 0.041 b 0. 17 0. 20 0. 27 0. 00 7 0 .0 0 8 0.011 c 0. 09 -- - 0. 20 0. 00 4 --- 0.008 e 0 .5 0 bs c 0.020 bsc d 14 .00 b s c 0.551 bsc d 1 12 .00 b s c 0.472 bsc e 14 .00 b s c 0.551 bsc e 1 12 .00 b s c 0.472 bsc l 0. 45 0. 60 0. 75 0.0 1 8 0.0 2 4 0.030 l 1 1. 00 ref 0.039 ref r1 0. 08 0. 15 -- - 0.0 0 3 0.0 0 6 --- r2 0. 15 0. 20 0. 25 0.0 0 6 0.0 0 8 0.010 s 0. 20 -- - -- - 0.0 0 8 -- - -- - 0 3. 5 7 0 3. 5 7 1 0 -- - -- - 0 - -- - -- 2 11 12 13 11 12 13 3 11 12 13 11 12 13 not e : 1. dim e n s i on of d1 a n d e 1 do no t in cl ud e mo ld p r ot ru si on. allo w abl e pro t r u sio n is 0 . 25m m pe r si d e . dim e n s i on d1 a n d e 1 are ma xim u m p l ast i c bod y s i ze dim e n s io ns inclu d i n g m o ld m i smat ch . 2. dim en s io n b do es n ot i n clu de d am b ar pr ot ru si on. al low ab l e dam b ar pro tru si o n sh all not cau s e th e l e ad w i dt h to e xcee d . da m b a r can n o t be lo cat e d on th e lo wer r a dius or th e lea d ro o t. 3. cont r o lli ng dimensi on : mi llimeter. 4 . a1 is d e f in ed a s t he dista n ce fr om the sea t in g p l a n e t o th e lo we st po in t of t h e p a cka g e bo d y .
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 38 r ev. a 0 2 /05 /20 08 TW8817 register summary t h e re gisters a r e o r g anized in fu nct i ona l g r o u p s in t h is re g i st er s u m ma r y . a r e gister c o n tai ni ng dif f er ent fun c t i on al bit s m a y a p p e a r more t han o n ce in d i ffere n t f unction al grou ps. if a p a r tic ular bit o f a reg i ste r is n o t re la ted to t hat f unc tio na l gro u p , it is p r i n t ed in sm a lle r fo nt t h a n th o s e re la te d. for e x a m pl e, bi t 7 of index 00 6 is cla ssif i e d a s ?ge n e r al ? an d is p r int ed in norm a l size ; t he o t h e r b i ts in this re giste r are p r in ted in s m aller size fo r the ir funct i ona lit y is n o t classif i e d a s ?g e nera l ? . g enera l index (hex) 7 6 5 4 3 2 1 0 reset value 000 i d rev 49h xf f * * * * * * * pa ge_1 00h decoder index (hex) 7 6 5 4 3 2 1 0 reset value 001 v d lo ss h lo c k s l o ck fi e l d v l o ck c cva li d m o no de t 5 0 00h 002 - fc2 7 if sel y s el - - 40h 003 - - 004 - ck hy - 00h 005 - - 006 sre se t pdy b f vref ag c_ en cl kpdn y _ pdn c_ p dn v_pdn - 007 vd ela y _ h i v a c tive_h i hd el a y _ h i h act i v e_h i 12h 008 vde la y _lo 12h 009 va ct iv e_l o 20h 00a hd el ay _l o 10h 00 b ha c t i ve _l o d0h 00 c p b w d em p a l s w se t7 c o m b hc o m p y c o m b pdl y cch 00 d * * w sse n cc odd l i n e 15h 00e cr ce rr w s s f l d w s s 1 - 00f ws s 2 - 010 b ri g ht ne ss 00h 011 co nt ra s t 5ch 012 s cur ve vs f ct i s h a rp ne ss 11h 013 sa t_u 80h 014 sa t _v 80h 015 h ue 00h 016 - - 017 shc or - vs hp 30h 018 c t co r c co r v c or ci f 44h 019 de l t a _ n i nre fi i n re fv s av e 00 h 01a c cva li d _ en eds _e n c c _e n pa ri t y f f _o v f ff _ em p c c_e ds lo _ h i 00h 01 b cc_d at a - 01 c dt s t us s t dn o w a t r e g s t and ard 17h 01 d s t a r t pal60 p a l c n p a l m nt sc4 se ca m pal b nt s c m 7fh 01e - cv s t d cv fm t 08h 01f t est 00h
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 39 r ev. a 0 2 /05 /20 08 decoder (cont.) index (hex) 7 6 5 4 3 2 1 0 reset value 020 cl p e nd cl pst 50h 021 nm ga i n w p g a i n ag cga i n 8 42h 022 ag cg ai n f0h 023 pe ak w t d8h 024 cl m pl d cl m p l bch 025 s y nc t d sy nc t b8h 026 m i ss cnt hs w i n 44h 027 pc lam p 2ah 028 v l ck i vl ck o vm ode de tv a f l d v i nt 00h 029 bs ht v sh t 00h 02a cki l lm ax ck i l lm i n 78h 02 b ht l v t l 44h 02 c ck lm y dl y hf lt 30h 02 d hp l c ev cn t p a lc s de t tb c _e n by pa ss sy ou t ha dv 14h 02e hpm a c ct sp m cb w a5h 02f nki l l pk i ll s ki l l cba l f cs lcs c cs bs t e0h 030 s i d_f a il pid_ fa i l f s c _ f a i l sloc k_f ail csb a d m vcsn cs t ri p e c t y p e - 031 v cr w kai r w ka i r1 vs td n i ntl w ss det e d s d et ccd et - 032 h f ref / g va l / p he r rdo / c g ai n o / ba m po / m i na vg/ s y t h rd / sy am p - 033 f rm y nr c lm d ps p 05h 034 ind ex n sen / s sen /p s e n / w k th 1ah 035 c t e st y c l en ccl en vcl en g t es t vlp f c kl y c k l c 00h 03 6-3 7 - 038 d ec_ sel - - - f b py fb pc f b pv mix 80h
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 40 r ev. a 0 2 /05 /20 08 lcdc ? input control index (hex) 7 6 5 4 3 2 1 0 reset value 040 ofdm rvoddp slvsfld ecsync de_pol hs_pol vs_pol ck_pol 00h 041 ecoast coast_p exp_de de/hs# * dtvck_delay 20h 042 vgafld selfvs vsdl_656 selfths cr601 input_data_bus_routing 04h 043 pllos * pckcap * * decpol 22h 044 coast_range * b8601 ip_color_fmt ip_sel 08h 045 ofd_det_end ofd_det_st 54h 046 csync_vs_offset 20h 047 ip_ha_st_lo 00h 048 ip_ha_end_lo cfh 049 ip_ha_end_hi * ip_ha_st_hi 20h 04a ip_va_st_odd_lo 13h 04b ip_va_st_evn_lo 13h 04c ip_va_length_lo 00h 04d * ip_va_length_hi ip_va_st_evn_hi ip_va_st_odd_lo 30h 04e * gpioen2 gpioen1 gpioen0 irq_al * * * 00h 04f gpio1_p gpio1_src gpio1_d gpio0_p gpio0_src gpio0_d 00h lc dc ? inp u t measureme n t index (hex) 7 6 5 4 3 2 1 0 reset value 050 * 00h 051 mea_win_h_st_lo 20h 052 mea_win_h_end_lo ffh 053 mea_win_h_end_hi * mea_win_h_st_hi 10h 054 mea_win_v_st_lo 20h 055 mea_win_v_end_lo fah 056 * mea_win_v_end_hi * mea_win_v_st_hi 00h 057 result_0 - 058 result_1 - 059 result_2 - 05a result_3 - 05b result_sel field_sel rd_lock mea_st 00h 05c u_27m noise_mask err_toler chg_det 00h 05d threshold_for_act_det enalu nofsel * 30h
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 41 r ev. a 0 2 /05 /20 08 lcdc - scaling index (hex) 7 6 5 4 3 2 1 0 reset value 060 x_scale_up_mid b4h 061 x_scale_down_lo 80h 062 y_scale_up/down_mid 50h 063 pa no ra _m a * * z o o m bp y _ sc al e_u p/do w n _hi y _sca le _ up / do w n _ mi x_ s ca l e_ do w n_ h i x_ s ca l e_ up _ hi 00 h 064 x_offset 00h 065 y_offset_even 80h 066 h_non_display_pixel / h_panorama_pixel 00h 067 lb_ce * * * * * h _ no n_ di s p la y / h_ panor m an _p ixel 00 h 068 x_scale_up_lo (at_the_side_for_panorama) 00h 069 x_scale_up_lo 00h 06a y_scale_up/down_lo 00h 06b y_offset_odd 00h lc dc ? im age adjustment index (hex) 7 6 5 4 3 2 1 0 reset value 070 * indx_cb hue 20h 071 contrast_r / contrast_y 80h 072 contrast_g / contrast_cb 80h 073 contrast_b / contrast_cr 80h 074 brightness_r / brightness_y 80h 075 brightness_g 80h 076 brightness_b 80h 077 h_sharp_cor h_sharpness 3fh 078 h _ s h ar p_f re q * dynr hflt 0ah 079 * * * * - 07a * - 07b * * * - 07c t_bw * pedlvl whtlvl ubtilt uwtilt bpbw * 1ch 07d bw_line_st_lo 08h 07e bw_line_end_lo f6h 07f bw_line_end_hi bw_line_st_hi 08h 080 bw_h_delay 10h 081 * bw_h_filter_gain 0dh 082 * bw_v_filter_gain 03h 083 bw_ldiff 00h 084 bw_black_tilt 67h 085 bw_white_tilt 94h 086 bw_black_limit 18h 087 bw_white_limit e8h 088 bw_mode * cah 089 * bw_gain 02h 08a * * * bw_stroff 0ah 08b * * * bw_strhys 04h
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 42 r ev. a 0 2 /05 /20 08 lcdc ? osd index (hex) 7 6 5 4 3 2 1 0 reset value 090 * * * * * * * * - 091 * * * * * * * * - 092 * * * * e_ v dly 06h 093 * * * * * * * * - 094 f _ r a m it a l ic und er_l i ne c bs_en fr_ add [ 1 :0 ] fr a m _ c l fr_r ac_ sel 00 h 095 w 1 e n d vb end c h _ e x t r d978 _s el * * * * 00h 096 s eri a l _b us _o sd _ ram _a ddr [ 7: 0] 00h 097 se ri a l _b us _o s d _ra m _d at a _hi ( f ont d at a) - 098 s eri a l _b u s _ o sd _ ram _d a t a _ lo ( f o nt at t r i b ut e ) - 099 se ri a l _ b us _ f on t _ ram _a dd r 00h 09a se ri a l _b us _ f on t _ ram _da t a - 09 b st a r t _s ra m _a d d res s 31h 09 c ra m_ d1 6 * * o s d_ of f ch _c olor_l oo ku p _ add r 00h 09 d ch _c olor_l oo ku p_d a t a 00h 09e w i n_ a l p h a_c o l o r_s el * * w i n _con_ sel 00h 09f w i n _c w i n_r w i n_g w i n_b w i n_3d wi n _ e 3 d wi n _ e 3 l wi n _ e n 00h 0a 0 * * w i n _ v_ st [9 :8 ] * w i n _ h _ s t [1 0 : 8 ] 00h 0a 1 w i n_ h_st [ 7 : 0] 00h 0a 2 w i n_v_st[7 : 0 ] 00h 0a 3 * * w i n_ w i d t h 00h 0a 4 * * w i n_h e ight 00h 0a 5 w i nbc_e n w i nbc_ r w i nbc_g w i nbc_b w i nbc_ w i dth 00h 0a 6 w i nbc w i n_bord er_h_w i dth 00h 0a 7 * w i n_bord er_ v_ w i dth 00h 0a 8 w i n_ charac ter_ v_ spac e w i n_ch a ra ct er_h_ s p ac e 00h 0a 9 w i n_v_zo om w i n_ h_zoo m * * * * 00h 0a a w i n_ cnt_st_ addr [ 7 : 0 ] 00h 0a b w i n s _e w i ns _ r w i ns_g w i ns_b w i n_shad o w _w i dth 00h 0a c * * * * w i n_alph a _ ble n d i n g 00h 0a d w i nsc wi n m c _ e n cv _ex t w i nc_ bse_se wi n c _ s h ad _ c w i nc_sh ad_ r wi n c _ s h ad_ g w i nc_sh ad _ b 00 h 0a e * * * * w i n_ c_v _ s pace[4] w i n_ c_ h_ s pa ce[ 4 ] w i n _ sh a_ wi d t h [ 4 ] w i nbc_ w idth [ 4 ] 00 h
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 43 r ev. a 0 2 /05 /20 08 lcdc ? display control index (hex) 7 6 5 4 3 2 1 0 reset value 0b0 dblop fpdeah fphsah fpvsah rvfpck rvhilo rvbit fpclkc 40h 0b1 tcons * demode op6b trifp fpclk_delay 00h 0b2 fphs_period_lo 3ah 0b3 fphs_active_pw 10h 0b4 fp_h_back_porch 1bh 0b5 fpde_active_lo 00h 0b6 usereg fpde_active_hi fphs_period_hi 42h 0b7 fpvs_period_lo 26h 0b8 fpvs_active_pw 06h 0b9 fp_v_back_porch 1fh 0ba fp_v_active_lo 00h 0b b ea rl y _ s t fp_v_active_hi * fpvs_period_hi 33h 0bc * dither_option * dither_format 00h 0bd vsync_delay 08h 0be frclong frcshrt epwmx pwm_al vh_disha frerun autoc sdelvs 00h 0bf disp_sngfld rvf_ac tvvsf4 noevni evndly 00h 0c0 ini_cnt_evn_lo 00h 0c1 ini_cnt_odd_lo 00h 0c2 ini_cnt_evn_hi ini_cnt_odd_hi 00h 0c3 evnpm number_of_lines_to_black_out 00h 0c4 pwmc_d2 pwm_counter 40h 0c5 00 h 0c6 00 h 0c7 pwm2c_d2 pwm2_counter 40h 0c8 mcudbg l adc_ pd _c m p l a d c _ p d l adc_ d i v[ 2 : 0 ] 00 h 0c9 ladc0[7:0] 00h 0ca ladc1[7:0] 00h lc dc ? statu s & in terrupt index (hex) 7 6 5 4 3 2 1 0 reset value 0d0 lb_ovf lb_unf v_los_c h_los_c vdlos_c v_loss h_loss syncs - 0d1 m_rdy pws_c v_prd_c h_prd_c lbounf vdc_c vh_los_c syncs_c - 0d2 irq_b_b17 irq_b_b16 irq_b_b15 irq_b_b14 irq_b_b13 irq_b_b12 irq_b_b11 irq_b_b10 ffh 0d3 * * ir q_b_ v d ir q_ b _ c c ir q_ b _ 5 0 0 7 h lc dc ? po wer man agemen t index (hex) 7 6 5 4 3 2 1 0 reset value 0d4 divde_down_counter_msb 00h 0d5 pclk_pdn en_pin5 pwr_state manpwr edpms pwr_state_wt 00h 0d6 suspend_stdby_cnt on_suspend_cnt 00h 0d7 off_stdby_cnt stdby_off_cnt 00h 0d8 stdby_suspend_cnt suspend_on_cnt 00h
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 44 r ev. a 0 2 /05 /20 08 lcdc ? color enhancement index (hex) 7 6 5 4 3 2 1 0 reset value 0da ce_center0 3dh 0db ce_center1 c3h 0dc ce_center2 fch 0dd ce_en ce_spread0 ce_gain0 00h 0de * ce _s p rea d 1 ce _ g ai n 1 00 h 0df * ce_spread2 ce_gain2 00h lc dc ? et c index (hex) 7 6 5 4 3 2 1 0 reset value 0e0 llbf selfcnt * sacnt * * * wr_sqnc_en 40h lc d c ? g a mma index (hex) 7 6 5 4 3 2 1 0 reset value 0f0 gamae_r gamae_g gamae_b * auto_inc gamma_rgb_indx 00h 0f1 gamma_ram_starting_addr 00h 0f2 gamma_ram_data - 0f3 - gainy[8] 00h 0f4 gainy[7:0] 00h da c index (hex) 7 6 5 4 3 2 1 0 reset value 0f5 d a _rga i n [ 4 : 0 ] 00 h 0f6 da _ g gai n[ 4 : 0] 00 h 0f7 d a _ b ga i n [4 : 0 ] 00 h 0f8 dac pd - daciref 00h s spl l index (hex) 7 6 5 4 3 2 1 0 reset value 0f9 clk_sel - - fpll[19:16] 00h 0fa fpll[15:8] 40h 0fb fpll[7:0] 00h 0fc fss[7:0] 40h 0fd pd_sspll ssd ssg 30h 0fe post vco - ipmp 11h
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 45 r ev. a 0 2 /05 /20 08 ccfl control index (hex) 7 6 5 4 3 2 1 0 reset value 130 oven oien uien fben lockv lockh ccflenb ccflden f2h 131 lvt lilt lit adh 132 le d_p d le dc _ di g _e n ccfl_st lstp 04h 133 fpwm 80h 134 fdim 84h 135 f pb i as_ e n l edc_o u t _ sel ccfl_ ou t_ sel ddim 00h 136 pwmtop 20h 137 - lp_x8 lp_x4 cp_x4 00h test con trol and g p o index (hex) 7 6 5 4 3 2 1 0 reset value 01f test_mode 00h 140 pwm2_en gpo6_en gpo5_en gpo4_en gpo3_en gpo2_en gpo1_en gpo0_en 00h 141 - gpo6_o gpo5_o gpo4_o gpo3_o gpo2_o gpo1_o gpo0_o 00h 142 00 h 143 00 h 157 counter_read_byte_0 - 158 counter_read_byte_1 - 159 counter_read_byte_2 - 15a counter_read_byte_3 -
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 46 r ev. a 0 2 /05 /20 08 tcon index (hex) 7 6 5 4 3 2 1 0 reset value 175 * cl p w p o l_ ste p 00h 176 * g p i o _ p ix _ h [ 3 :0 ] 00h 177 gp i o _p i x _l[ 7: 0] 5ah 178 * gp i o _ li ne _h [ 3: 0] 00h 179 gp i o _ li ne _l[ 7: 0 ] 7fh 17a * gp i o _ f ram e [ 2: 0] 01h 17 b gpio_c o n l i n e _con s y n c _con [ 1 : 0 ] cl p s e l [ 1 :0 ] c s psel [ 1 : 0 ] 00h 180 gpi o _0 t c ck _p h ro e _e n * di v _ ck 20h 181 * p o l_c on d e l t a _li n e _ con de l t a _ l i n e _ en r ev_en * in v 00 h 182 * to p_b tm lf t_rht 05h 183 * rc k _ p r o e _ p r sp_p cl p_ p c sp_p 1fh 184 * p gm _r ck pg m _roe pg m _rsp p g m _cp p gm _c lp p g m _cs p 00h 185 * i n v _ sw 00h 18a * rsp _ w i d t h * co m pa ny 02h 18 b rev v _ rev c 4dh 18 c * v_s t [ 1 1 : 8] 00h 18 d v_ st [ 7: 0 ] 06h 18e * v_ e d[ 1 1: 8] 01h 18f v_ ed[ 7 : 0 ] e2h 190 cp _s w [ 11 : 8] 02h 191 cp _s w [ 7 : 0] d0h 192 * l p _s t[11: 8 ] 02h 193 lp _ s t[ 7: 0] d0h 194 * lp _e d [ 11: 8] 00h 195 lp _ e d [ 7: 0] 06h 19a * sp_ st[ 1 1 : 8 ] 00h 19 b sp _s t [ 7: 0] c8h 19 c * sp_ ed [ 11 : 8 ] 00h 19 d sp_ e d [7 : 0 ] 01h index (hex) 7 6 5 4 3 2 1 0 reset value 1a 0 * c sp_s t [ 11: 8 ] 00h 1a 1 c sp_s t[7: 0 ] 00h 1a 2 * csp _e d[ 1 1: 8] 02h 1a 3 c sp_ed [ 7 : 0 ] 30h 1a 4 * r sp_s t [ 11: 8 ] 00h 1a 5 06 h 1a 6 * rsp _e d[ 1 1: 8] 00h 1a 7 01 h 1a c * r o e_ st[11 : 8 ] 00h 1a d 0a h 1a e * r o e _ ed [ 11 : 8 ] 00h 1a f r o e_ ed [ 7 : 0 ] 36h 1b 0 * r ev_in v l i n e _ i nv 02h
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 47 r ev. a 0 2 /05 /20 08 lcdc ? sense index (hex) 7 6 5 4 3 2 1 0 reset value 1b1 * * bias_ctl * 00h 1b2 - 1b3 - 1b4 - t e s t c o n trol index (hex) 7 6 5 4 3 2 1 0 reset value 1f0 pccinia_index frc_2f frc_1f pccinia_sub_indx 00h 1f1 pccinid 00h 1f2 - 1f3 sel_c grayd data_0 * * * romsft ramsft 00h mc u sfr r e gi s t er index (hex) 7 6 5 4 3 2 1 0 reset value 0x9a * bank_sel[5:0] 00h 0x9b * sclk_sel[1:0] lowspd host_s1 host_s0 dual 00h 0x9c t0_div_h[7:0] 00h 0x9d t0_div_l[7:0] 90h 0x9e t1_div_h[7:0] 00h 0x9f t1_div_l[7:0] 90h 0x93 t2_div_h[7:0] 00h 0x94 t2_div_l[7:0] 90h
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 48 r ev. a 0 2 /05 /20 08 w8817 registers description 0x000 ? product id code register (id) bit function r/w description reset 7-3 id r the TW8817 product id code is 01001. 01001b 2-0 revision r revision number 001b 0x 001 ? ch i p sta t us register (cstatus) bit function r/w description reset 7 vdl os s r 1 = video n o t p r e s e n t. ( s y n c is n o t de t e ct ed i n nu m ber o f con secu t i v e li n e pe r i od s spe cifi e d by m i ss cnt r e g i s t er ) 0 = video d e t e c t e d . 0 6 h lo c k r 1 = h or i z o n t al s y nc p ll i s l oc k ed t o t h e i nc o m i n g v i deo s our c e. 0 = h or i z o n t al s y nc p ll i s n ot l oc k e d. 0 5 s l o ck r 1 = s u b - c ar r i er p l l i s l oc k ed t o t h e i n c o m i n g v i d eo s our c e. 0 = s u b - c ar r i er p l l i s n ot l oc k e d. 0 4 field r 0 = odd fi e l d i s be i n g d e c o ded. 1 = ev e n fie l d is b e i ng de coded . 0 3 v l o ck r 1 = v er t i c al l o gi c i s l o c k e d t o t h e i nc omi n g v i de o s our c e. 0 = v er t i c al l o gi c i s not l o ck e d . 0 2 reserved r reserved 0 1 m o n o r 1 = no co l o r bu r s t signa l de t e ct ed . 0 = c ol or bur st s i g nal d et ec t ed. 0 0 de t 50 r 0 = 6 0 h z s o ur c e det e c t e d 1 = 5 0 h z s o ur c e det e c t e d the a ct u a l v e r t ica l scann i n g fr eq uenc y d epen ds on t he cu rr e n t standa r d i n v o k e d . 0 0x 002 ? input format (i n f o r m) bit function r/w description reset 7 reserved r/w reserved 0 6 fc27 r / w 1 = i npu t c r y s ta l c l o ck fr e quen cy i s 27 m h z. 0 = s q uar e pi x el mo d e. m ust u s e 2 4. 5 4m hz f or 60 hz f i el d r at e s our c e or 2 9 . 5m h z f or 5 0h z f i el d r at e s o ur c e. 1 5 - 4 ifs e l r / w 11 = co m pone nt vi d e o decod i n g (p rog r e ssiv e i npu t) 10 = co m pone nt vi d e o decod i n g (i nte r l a ce i npu t) 0 1 = s - v i deo d ec o di n g 00 = co m pos i t e v i d eo de c od i ng 00 3- 2 y s e l[ 1 : 0] r/ w t h es e t hr e e bi t s c o nt r ol t h e i n p ut v i de o s el e ct i on. i t s e l e ct s t he c omp o s i t e v i de o s o ur c e or l u m a sou r ce . 00 : y o ut = y i n 0 01 : y o ut = y i n 1 10 : y o ut = y i n 2 (c i n ) 11 : n o t e x i s t 00 1 reserved r/w reserved 0 0 reserved r/w reserved 0
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 49 r ev. a 0 2 /05 /20 08 0x003 ? reserved bit function r/w description reset 7-0 reserved r/w reserved - 0x 004 ? h s ync del a y c ontrol bit function r/w description reset 7 reserved r/w reserved 0 6- 5 ck hy r/ w c ol or ki l l er t i me c o n s t a nt 0: f as t 3: s l o w 0 4-0 reserved r/w reserved 0 0x005 ? reserved bit function r/w description reset 7-0 reserved r/w reserved - 0x006 ? analog control register (acntl) bit function r/w description reset 7 sr eset w a 1 w r i tte n t o t h i s b i t r e se t s t h e de v i ce t o its d e f au lt st a t e bu t a l l reg i st e r con t e n t r e m a i n unchan ged . th is b i t i s s e l f-r e s e t ting . 0 6 p d y b f r/ w 0 = p ow er d ow n y + c o ut p ut b uf f er 1 = p o w e r do w n (de f au l t) 1 5 v r e f r / w 0 = in te rn a l v o l t a g e re fe re n c e . 1 = in te rn a l v o l t a g e re fe re n c e sh u t d o w n . 0 4 agc_ en r / w 0 = agc l oop f un c tion en ab l ed . 1 = a g c l o o p f u nc t i o n di s abl ed. g ai n i s s et t o by ag c g a i n. 0 3 c lk _p dn r/ w 0 = n or m a l c l o c k o per at i o n. 1 = 2 7 m h z cl oc k i n pow er d ow n mo de. 0 2 y _ pd n r / w 0 = lum a a d c i n n o r m a l ope r a tion . 1 = lum a a d c i n p o w e r do w n m o de . 0 1 c _p d n r/ w 0 = c hr o ma a d c i n n or m a l op er at i o n . 1 = ch r o m a a d c i n po w e r do w n m ode . 0 0 v_p d n r / w 0 = v chann e l adc i n no r m a l ope r a t i on . 1 = v chann e l adc i n po w e r d o w n m ode. 0 0x007 ? cropping register, high (crop_hi) bit function r/w description reset 7-6 vdelay_hi r/w these bits are bit 9 to 8 of the 10-bit vertical delay register. 00 5- 4 v a c ti v e _ hi r/ w t h es e bi t s ar e bi t 9 t o 8 of t h e 1 0- bi t v a c ti v e r e gi s t er . r ef er t o d e s c r i pt i o n on r e g0 9 f or i t s shado w r e g i s t e r . 01 3-2 hdelay_hi r/w these bits are bit 9 to 8 of the 10-bit horizontal delay register. 00 1-0 hactive_hi r/w these bits are bit 9 to 8 of the 10-bit hactive register. 10 0x008 ? vertical delay register, low (vdelay_lo) bit function r/w description reset 7- 0 vde l a y _lo r/ w t h es e bi t s ar e bi t 7 t o 0 of t h e 1 0- bi t v er t i c al d el ay r egi st er . t he t w o m s bs ar e i n t h e cr o p _hi reg i st e r. it defines t h e num ber of li ne s be t w een the l e ad i n g edge of vsy n c and t h e st ar t of t h e ac t i v e v i de o. 12h delete d : a nd hsync d el a y c o n tro l
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 50 r ev. a 0 2 /05 /20 08 0x009 ? vertical active register, low (vactive_lo) bit function r/w description reset 7- 0 va ct i v e _ lo r/ w t h es e bi t s ar e bi t 7 t o 0 of t h e 1 0- bi t v er t i c al a c t i v e r e gi s t er . t h e t w o m sb s ar e i n t h e cr o p _hi reg i st e r. it de fines t h e nu m ber o f a ctiv e vid e o l i nes pe r fr am e ou t p u t . t h e va c t i v e r e gi s t er ha s a s h ad o w r egi s t e r f or us e w i t h 5 0hz s o ur c e w h en a t r e g of reg 0 x 1 c i s no t set. th i s r e g i st e r can be acces s e d t h rough t h e sam e i n d e x a d d r e ss b y fir s t chang ing t he f o r m a t s t and a r d t o an y 50 hz s t and a r d . 20h 0x00a ? horizontal delay register, low (hdelay_lo) bit function r/w description reset 7- 0 hde lay _ lo r/ w t h es e bi t s ar e bi t 7 t o 0 of t h e 1 0- bi t h or i z o nt a l d el ay r egi st er . t h e t w o m s bs ar e i n t h e c r op _h i regi st er. it defines t h e number of pix e l s bet w een t h e l e adi ng edge o f t h e hsy nc and the star t o f the i m age cr oppi n g f o r acti v e v i deo. the hd e l a y _l o r e g i s t e r has tw o s hado w re g i s t e r s f o r u se w i th p a l a n d se c a m sou r ces r es pe c t i v el y . t he s e r egi st er c an b e ac c e s s e d u s i n g t he s ame i n d ex ad dr es s by f i r s t chang ing t h e de cod i ng f o r m at to t he co rr e s p ond ing standa r d . 10h 0x00b ? horizontal active register, low (hactive_lo) bit function r/w description reset 7- 0 ha c t i v e _ lo r/ w t h es e bi t s ar e bi t 7 t o 0 of t h e 1 0- bi t h or i z o nt a l a c t i v e r e gi s t e r . t he t w o m s bs ar e i n t h e cr o p _hi reg i st e r. it defines t h e num ber of activ e p i xe l s per l i ne output. d0h 0x00c ? control reg iste r i (cn t rl1) bit f unc t i o n r/w de scri ption reset 7 pb w r/ w c o mbi n ed w i t h v t l[ 3] , t h er e ar e f o ur di f f er e nt c hr oma ba n dw i dt h c a n b e s el e ct e d. 1 = w i de c hr o m a bp f b w 0 = no r m al chroma bpf bw 1 6 dem r / w co l o r k i ll e r s e nsiti v i t y . 1 = lo w 0 = h i gh 1 5 pa ls w r/ w 1 = pa l s w i t c h s e ns i t i v i t y l o w . 0 = pa l s w i tch sensitivity normal. 0 4 set7 r/ w 1 = t h e bl ac k l ev el i s 7. 5 i r e ab ov e t h e bl a nk l e v el . 0 = t h e bl ac k l ev el i s t he s a me as t h e bl ank l ev el . 0 3 com b r / w 1 = adap tiv e c o mb fil t e r on f o r nt sc /pal 0 = n ot c h f i l t er 1 2 hco m p r / w 1 = ope r a t i o n m o de 1 . ( r e co m m ended ) 0 = o p er at i o n m o d e 0. 1 1 ycomb r/ w t hi s bi t c o nt r ol s t h e c omb o per at i o n w hen t h er e i s n o c ol or bur st . 1 = no c o m b . 0 = c o mb. 0 0 pdl y r / w pal de la y l i n e . 0 = enab led . 1 = d i sab l ed . 0 0x 00d ? cc contro l bit f unc t i o n r/w de scri ption reset 7- 6 res er v e d r/ w r es er v e d 5 w s s e n r/ w 1 = e n a bl e w s s d e c o di n g. 0 = di s abl e d. 4 - 0 c c o ddl i n e r / w the s e b i t s con t r o l the c l o sed c aption decod ing li ne num b e r i n case o f odd fi e l d 15h del e t ed: 0x 0 d ? v e rtic a l s c al i ng re gi st er , low ( v scal e _ l o )? bi t ... [1]
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 51 r ev. a 0 2 /05 /20 08 0x00e ? wss1 bit function r/w description reset 7 c r c e r r r th i s i s the crc e r r o r i n d i cat o r f o r 52 5 - li ne w ss. 1 :c r c e r ro r . 0 :n o e rro r - 6 wssfld r these bit indicates the detected wss field information, 0=odd and 1=even. - 5-0 wss1 r these bits represent the sliced wss data bit 13 to 8. - 0x00f ? wss2 bit function r/w description reset 7-0 wss2 r these bits represent the sliced wss bit 7 to 0. - 0x010 ? brightness control register (bright) bit function r/w description reset 7- 0 br i g ht nes s r/ w t h es e bi t s c o nt r ol t h e br i g ht nes s. t h ey h av e v al u e of ? 12 8 t o 12 7 i n 2 ' s c o m p l e me n t f or m . p o si t i v e v al u e i nc r e a s es br i g ht n es s . a v al u e 0 h as n o ef f ec t o n t h e d at a. 00h 0x011 ? contrast control register (contrast) bit function r/w description reset 7 - 0 c o n t r a st r / w the s e b i t s con t r o l the c o n t r a st. the y ha v e v a lue o f 0 t o 3 . 98 ( ffh ). a v a lue o f 1 (`100_ 0000 `) has no e f f e ct on the v i d e o dat a . 5ch 0x012 ? sharpness control register i (sharpness) bit function r/w description reset 7 s cur v e r / w th i s bi t con t r o l s t h e c e n t e r fr e quen cy o f the peaking fil t e r. the co rr e s p ond i n g gain ad j u s t me n t i s hflt . 0 = low 1 = c ent er 0 6 vs f r/ w t hi s bi t i s f or i nt er nal us e d. 0 5- 4 ct i r/ w c ol o r t r a n s i e nt i m pr o v eme n t l ev el c o nt r ol . t her e ar e 4 e n ha n c e m en t l ev el s w i t h 0 b e i n g t h e l ow es t a nd 3 b ei n g t he hi gh e s t . 1 3 - 0 s h arp r / w the s e b i t s con t r o l the am ount o f sha r pn e s s enh ancem en t on the l u m i n ance si gna ls. th e r e a r e 16 l e v e l s o f c o n t r o l w i th '0' ha v i n g no e f f e ct on t h e ou t p u t i m ag e and '15' b e i ng t h e stronge st. 1 0x 013 ? chroma (u) gain register (sat_u) bit f unc tion r/w description reset 7 - 0 sat_u r/w these bits control the digital gain adjustment to the u (or cb) component of the digital video signal. the color saturation can be adjusted by adjusting the u and v color gain components by the same amount in the normal situation. the u and v can also be adjusted independently to provide greater flexibility. the range of adjustment is 0 to 200%. 80h 0x 014 ? chroma (v) gain register (sat_v) bit f unc tion r/w description reset 7 - 0 sat_v r/w these bits control the digital gain adjustment to the v (or cr) component of the digital video signal. the color saturation can be adjusted by adjusting the u and v color gain components by the same amount in the normal situation. the u and v can also be adjusted independently to provide greater flexibility. the range of adjustment is 0 to 200%. 80h del e t ed: 0x0f ? horizontal scaling register, low (hscale_lo)?
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 52 r ev. a 0 2 /05 /20 08 0x015 ? hue control register (hue) bit function r/w description reset 7 - 0 h u e r / w the s e b i t s c o n t r o l the c o lo r hue. it is in 2 ? s co m p l e m ent fo r m w i th 0 be i n g the cen t e r v a l u e . pos i tiv e v a lue r e su l t s i n r e d h u e an d nega tiv e v a l u e g i v e s g r e e n hue . 00h 0x017 ? vertical peaking control i bit function r/w description reset 7- 4 sh co r r/ w t h es e bi t s pr ov i de c or i ng f u n c t i on f or t h e s h ar p n es s c o n t r ol . 3h 3 reserved r/ w reserved 0 2 - 0 v s h p r / w ve rti ca l peak i n g ga i n c o n t r o l 0 0x018 ? coring control register (coring) bit function r/w description reset 7- 6 ct co r r/ w t h es e bi t s c o nt r ol t h e c or i n g f u n c t i o n f or t h e c t i . i t has i nt er n al s t e p s i z e of 2. 1h 5 - 4 c c o r r / w the s e b i t s con t r o l the l o w l e v e l c o ri ng func ti on fo r t h e cb / c r ou tpu t. 0h 3 - 2 v c o r r / w the s e b i t s con t r o l the c o ring f unc ti o n o f t h e v e rtica l peak i n g l o g i c. it h a s an i n te r n a l s t ep s i ze of 2. 1h 1 - 0 c i f r / w the s e bi t s con t r o l the if c o m pensation l e v e l . 0 = no ne 1 = 1 . 5 d b 2 = 3 d b 3 = 6 d b 0h 0x019 ? delta rgb mode and adc control register bit function r/ w description re set 7 res er v e d r/ w reserved 0 6 de l t a _ n r/ w delta rgb mode enable 0 4 i nre fi r/ w adc bias current control (0 = normal) 0 3 i nre fv r/ w adc voltage reference (0 = normal) 0 2 s a v e r / w adc r educe supp ly c u r r e n t ( 1 = sa v e ) 0 1- 0 res er v e d r/ w reserved 0 0x01a ? cc/eds status register (cc_status) bit function r/w description re set 7 ccv a li d en r/ w 0 6 eds _ e n r/ w 0 = e ds d at a i s not t r an s f er r e d t o t h e c c_ da t a fi fo . 1 = eds data is transferred to the cc_data fifo. 0 5 cc _e n r/ w 0 = c c d a t a i s not t r an s f er r e d t o t h e c c_ da t a fi fo . 1 = cc data is transferred to the cc_data fifo. 0 4 pa ri t y r 0 = d at a i n c c _ d ata ha s no er r or . 1 = data in cc_data has odd parity error. - 3 ff _ o v f r 0 = a n ov er f l ow ha s n ot oc c ur r e d. 1 = an overflow has occurred in the cc_data fifo. - 2 f f_e m p r 0 = cc _da ta f i fo i s em pty . 1 = cc_data fifo has data available. - 1 cc _e d s r 0 = cl o s e d c a pt i o n d at a i s i n c c_ d at a r e gi st er . 1 = extended data service data is in cc_data register. - 0 lo _h i r 0 = low b y t e o f t he 1 6- bi t w or d i s i n t he c c _ da ta r eg i st er . 1 = high byte of the 16-bit word is in the cc_data register. - del e t e d :
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 53 r ev. a 0 2 /05 /20 08 0x01b ? cc/eds data register (cc_data) bit function r/w description reset 7-0 cc data r these bits store the incoming closed caption or even field closed caption data. - 0x 01c ? stan dard se lec t i o n (sdt) bit function r/w description reset 7 de ts t us r 0 = i dl e 1 = det ec t i o n i n pr o gr es s 0 6- 4 st d no w r c ur r ent s t an d ar d i nv o k e d 0 = nt sc (m ) 1 = p a l ( b ,d ,g ,h ,i ) 2 = se cam 3 = nt sc4 . 4 3 4 = pa l ( m ) 5 = pa l ( cn) 6 = pa l 6 0 7 = n o t va lid 0 3 a tr e g r / w 1 = d i sab l e t h e shado w re g i s t e r s. 0 = enab le v a ct i v e a nd hd el a y shad o w re g i s t e r s v a lu e de pend i ng o n st a nda r d 1 2 - 0 s t anda r d r / w stan da r d se l e c t i o n 0 = nt sc (m ) 1 = p a l ( b ,d ,g ,h ,i ) 2 = se cam 3 = nt sc4 . 4 3 4 = pa l ( m ) 5 = pa l ( cn) 6 = pa l 6 0 7 = a ut o det e c t i o n 7h 0x 01d ? stan dard recogni ti on ( s dtr ) bit function r/w description reset 7 a t st a r t r / w w rit i n g 1 to th is b i t wi l l m a n u a l l y i n it i a t e th e a u to fo rm a t d e te c t i o n p r o c e s s . t h i s b i t is a s e lf - re s e tt i n g b i t . 0 6 pal6_en r / w 1 = e nab le r e c o gniti o n of p a l60 . 0 = di s a bl e r e c o gn i t i on. 1 5 pa ln _ e n r/ w 1 = en a bl e r e c og n i t i on o f pa l ( cn) . 0 = di s a bl e r e c o gn i t i on. 1 4 pa lm _en r/ w 1 = en a bl e r e c og n i t i on o f pa l ( m ) . 0 = di s a bl e r e c o gn i t i on. 1 3 n t44_ en r / w 1 = e nab le r e c o gniti o n of n tsc 4 . 43. 0 = di s a bl e r e c o gn i t i on. 1 2 se c_ e n r/ w 1 = en a bl e r e c og n i t i on o f se ca m . 0 = di s a bl e r e c o gn i t i on. 1 1 p a l b _ e n r / w 1 = e nab le r e c o gniti o n of p a l ( b , d , g ,h,i). 0 = di s a bl e r e c o gn i t i on. 1 0 nt s c _e n r/ w 1 = en a bl e r e c og n i t i on o f nt s c (m ) . 0 = di s a bl e r e c o gn i t i on. 1
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 54 r ev. a 0 2 /05 /20 08 0x 0 1 e ? component video format (cvfmt) bit name r/w description reset 7 r sv r reserved 0 6 - 4 c v s t d r com p onent v i deo inpu t f o r m at de t e c t ion . 0 = 480i, 1 = 576i, 2 = 480p, 3 = 576p 0h 3 - 0 c v f m t r / w com p onent v i deo fo r m at se l e c t i o n . 0 = 480i, 1 = 576i, 2 = 480p, 3 = 576p, 8 = auto 8h 0x 01f ? t e s t contro l regi ster (test) bit function r/w description reset 7-0 test r/w t hi s r egi st er i s r es er v ed f or t es t i n g pur p os e . i n n or m al op er at i on, o nl y 0 s h o u l d be w r i t t e n i n t o t hi s r egi st er . 03h = d i g i t a l v i d eo de c o de r & r g b m i x d i re ct i npu t t e st th i s t e s t m o de a l l o w s d i g i t a l da t a to be i np ut f r o m dt v d [ 2 3: 0] pi ns t o t he i np ut of t h e di gi t al l o gi c of t h e v i d e o de c o d er ( r e pl a c e s y c a d c o ut put ) as t he c a s e w he n t h e c ont e n t s of t hi s r e gi s t er i s 0 4h. b esi des th is, t h e fpg1 /fpb1 /fpr1 p i ns be com e i n pu t s and p r o v id e da t a in p l a c e o f rg badc dat a o ut p u t . 0 4 h = di gi t al v i de o d ec od er di r e ct i n p u t t e s t t hi s t e s t mo d e al l o w s di gi t al dat a t o be i n p ut f r om dt v d pi n s t o t h e i n p ut of t h e di gi t al l o gi c o f t h e v i deo d e c o d er . ( r e pl a c e s a d c o ut p ut ) d tvd ( 2 3 - 16 ) > ? y ? de code r i n pu t da t a , dt v d ( 1 5 - 8 ) > ? u ? d e c od e r i npu t da t a d t v d (7 - 0 ) > ?v? de cod e r i npu t da t a 05h = c l o s e d c a p t i o n t e st m ode. 06h = y c adc t e s t m ode (dt v d p i ns be c o m e o u t p u t s) y c a d c d i g i t a l ou t p u t i s m a d e a v ai l abl e ex t er n al l y . ? y ? a d c o u t p u t d a t a > d t v d (1 5 - 8 ) , ? c ? & ?f b ? ad c o u tp u t d a ta > d t vd (7 -0 ) in de x - 1 f 3 - b i t- 7 = 1 > ?c ? da t a i n de x - 1 f 3 - b i t-7 = 0 > ?f b? da t a . 07h = d i g i t a l v i d eo de c o de r ou t p u t test (dt v d p i n s b e c om e ou tputs ) th e ou t p u t of t h e d i g i ta l v i de o d ec o der o ut p ut i s av ai l a bl e ex t er n al l y . ?r ? decode r ou t dat a > dtv d ( 2 3 - 16), ? g ? decode r ou t dat a > dtvd ( 1 5 - 8) ? b? dec od er o u t d at a > dt vd( 7- 0) ?v sy n c ? > cl a m p ? h sy n c ? > gpio[1 ] ?hac ti v e ? > gp io[0 ] 08h = r g badc t e s t m o de ( d tvd p i n s be c o m e ou tpu t s) rg b a dc d i g i ta l o u t pu t i s m ade a v a i lab l e e x te r n a l l y . ? g ? a d c ou t p ut dat a > dt v d( 1 5- 8) , ? b ? & ? r? a d c o u t put d a t a > d t v d( 7- 0) inde x - 1 f 3 - b i t-7 = 1 > ?b? da t a i nde x - 1 f 3 - b i t-7 = 0 > ? r ? da ta . 0 9 h = da c t es t m o de. d t v d[ 7: 0 ] i np ut s ar e r out e d t o t he da c d a t a i n p ut ? di n? . 0a h = a n al o g a dc cl amp t es t m o d e. dt v d[ 3: 0] i n p ut s ar e r o ut ed t o a d c cl a m p i ng c o n tr o l. 0 b h = d a c t e s t mo de . i n t e rna l gen era t e s inc r em enta l da ta f o r d a c d a t a inpu t. 1 1 h = t w 88 i n t er nal n od e t o f l at p a nel o ut p ut 0 0h del e t e d : 0 x19 ? vbi c on t r ol regi s t er ( v bi cntl) ?
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 55 r ev. a 0 2 /05 /20 08 0x020 ? clamping gain (clmpg) bit function r/w description reset 7 - 4 c l pend r / w the s e 4 b i ts set t h e e n d ti m e o f the c l am p i ng pu l se in t h e i n cr em ent o f 8 sy s t em c l o ck s . the clam pi ng ti m e is d e t e r m i ned b y th is t o g e t he r w i th cl pst . 5h 3- 0 clp s t r/ w t h es e 4 bi t s s e t t h e st ar t t i m e of t h e c l a m p i n g pul s e i n t h e i n c r e m en t of 8 s y s t em c l o c k s . i t i s r ef e r enc ed t o p c l am p p os i t i on. 0h 0x021 ? individual agc gain (iagc) bit function r/w description reset 7-4 nmgain r/w these bits control the normal agc loop maximum correction value. 4h 3-1 wpgain r/w peak agc loop gain control. 1h 0 agcgain8 r/w this bit is the msb of the 9-bit register that controls the agc gain when agc loop is disabled. 0 0x022 ? agc gain (agcgain) bit function r/w description reset 7- 0 ag cga i n r/ w t h es e bi t s ar e t h e l ow er 8 bi t s of t h e 9- bi t r egi st er t h at c o nt r ol s t h e a g c g ai n w he n a g c l o o p i s di s a bl e d. f0h 0x023 ? white peak threshold (peakwt) bit function r/w description reset 7-0 peakwt r/w these bits control the white peak detection threshold. d8h 0x024? clamp level (clmpl) bit function r/w description reset 7 clm pld r/ w 0 = cl a m pi ng l ev el i s set by clm pl. 1 = cl a m pi ng l ev el pr es et at 6 0 d. 1 6-0 clmpl r/w these bits determine the clamping level of the y channel. 3ch 0x025? sync amplitude (synct) bit function r/w description reset 7 s y nc t d r/ w 0 = r ef er e n c e s y nc a m pl i t u d e i s s et by sy nc t. 1 = r ef er e n c e s y nc a m pl i t u d e i s pr e s et t o 38 h. 1 6-0 synct r/w these bits determine the standard sync pulse amplitude for agc reference. 38h 0x026 ? sync miss count register (misscnt) bit function r/w description reset 7- 4 m i s scn t r/ w t h es e bi t s s et t h e t hr es h ol d f or h or i z o nt al s y nc m i s s c o u nt t hr e s h ol d . 4 h 3-0 hswin r/w these bits set the size for the horizontal sync detection window. 4h 0x027 ? clamp position register (pclamp) bit function r/w description reset 7-0 pclamp r/w these bits set the clamping position from the pll sync edge 2ah
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 56 r ev. a 0 2 /05 /20 08 0x028 ? vertical control i bit function r/w description reset 7 - 6 v l c k i r / w ve rti ca l l o ck in ti m e . 0 = f a s t es t 3 = sl o w e s t. 00 5 - 4 v l c k o r / w ve rti ca l l o ck o u t ti m e . 0 = f a s t es t 3 = sl o w e s t. 00 3 v m ode r/ w t hi s bi t c o nt r ol s t h e v er t i c al d e t ect i on w i nd ow . 1 = s e ar c h mod e . 0 = vertical count down mode. 0 2 d e t v r / w 1 = recom m end ed fo r spe ci a l app li c a ti on on l y . 0 = normal vsync logic 0 1 a fld r / w au t o fiel d gener a ti on cont r o l 0 = off 1 = o n 0 0 vi n t r/ w v er t i c al i nt e gr at i o n t i me c o nt r ol . 1 = nor mal 0 = s h or t 0 0x029 ? ve rti cal control ii bit f unction r/w description reset 7- 5 bsht r/w burst pll center frequency control. 0h 4 - 0 vsht r/w vsync output delay control in the increment of half line length 00h 0x 02a ? col or killer level control bit f unction r/w description reset 7 - 6 ckilmax r/w these bits control the amount of color killer hysteresis. the hysteresis amount is proportional to the value. 1h 5- 0 ckilmin r/w these bits control the color killer threshold. larger value gives lower killer level. 38h 0x 02b ? comb filter control bit f unction r/w description reset 7- 4 ht l r/w adaptive comb filter combing strength control. 4h 3- 0 vt l r/ w a d apt i v e c o m b f i l t er c o mbi n g st r en g t h c o nt r ol . hi g her v al ue pr ov i des st r on g er c o mb f i l t er i n g. 4 h 0x 02c ? luma delay and hfilter control bit f unction r/w description reset 7 ck lm r/ w c ol o r ki l l er mo de . 0 = n or m al 1 = f as t ( f or s p ec i al a p pl i c at i o n) 0 6- 4 ydly r/w luma delay fine adjustment. this 2's complement number provides ?4 to +3 unit delay control. 3h 3- 0 hflt r/w peaking control 2. the peaking curve is controlled by scurve bit. 0h
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 57 r ev. a 0 2 /05 /20 08 0x02d ? miscellaneous control register i (misc1) bit function r/w description reset 7 hplc r/w reserved. 0 6 evcnt r/w 1 = even field counter in special mode. 0 = normal operation. 0 5 palc r/w reserved. 0 4 sdet r/w id detection sensitivity. a ?1? is recommended. 1 3 tbc_en r/w 1 = internal tbc enabled. (test purpose only) 0 = tbc off. 0 2 bypass r/w it controls the standard detection and should be set to ?1? in normal use. 1 1 s y o u t r/ w 1 = h s y nc i s d i s a b l e d w hen v i de o l os s i s d et ec t ed. 0 = h s y nc i s a l w ay s ge n er at e d. 0 0 hadv r/w reserved. 0 0x 02e ? m isc e ll a neous con t ro l register ii ( m isc 2) bit function r/w description reset 7- 6 hpm r/ w h or i z o nt al p l l a c q ui s i t i o n t i me. 0 = s l o w 1 = med i um 2 = au t o 3 = fas t 2h 5 - 4 a cct r / w acc ti m e c o n st a n t 00 = n o acc 01 = s l o w 10 = m ed i um 11 = fa st 2h 3 - 2 s p m r / w b u rs t p l l co n tro l . 0 = sl ow es t 1 = sl ow 2 = f a s t 3 = f a s t es t 1h 1 - 0 c b w r / w ch r o m a l o w p a s s fil t e r band w i d t h c o n t r o l. 0 = low 1 = m edi u m 2 = hi g h 3 = n a 1h 0x 02f ? m i scell an eou s contro l iii (misc3 ) bit function r/w description reset 7 n k i ll r / w 1 = enab le no i sy s i gn a l co l o r k i ll e r f unc ti o n i n n tsc m ode . 0 = disabled. 1 6 pk i ll r/ w 1 = e n a bl e a u t o m at i c noi sy c ol or k i l l er f u nc t i on i n p a l mo de . 0 = disabled. 1 5 s k i l l r / w 1 = enab le au t o ma tic n o i s y c o lo r kil l e r f u n cti o n i n seca m m ode . 0 = disabled. 1 4 cba l r/ w 0 = n o r m a l o ut p ut 1 = special output mode. 0 3 f cs r/ w 1 = f or c e d ec o d er out p ut v al u e d et er m i n e d by ccs . 0 = disabled. 0 2 lcs r/ w 1 = e n a bl e pr e- d e t er m i n ed o ut p u t v al u e i n di c a t ed by c c s w he n v i d e o l os s i s d et e ct e d. 0 = disabled. 0 1 ccs r/ w w h en f cs i s s et hi g h o r v i de o l os s c on di t i o n i s d et e c t ed w hen l cs i s s et h i g h, o n e of t w o c o lo rs d i sp l a y ca n be se lect e d . 1 = b l ue c o l o r. 0 = black. 0 0 b s t r / w 1 = enab le b l ue s t re tc h. 0 = disabled. 0
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 58 r ev. a 0 2 /05 /20 08 0x030 ? macrovision detection bit function r/w description reset 7 si d _ fa i l r - 6 pi d _ fa i l r - 5 f sc_f a il r - 4 sl o ck _ fa i l r - 3 csb a d r 1 = m acr ov i s i on c ol or s t r i p e d et ec t i o n ma y b e u n- r el i a bl e - 2 m cvs n r 1 = m acr ov i s i on a g c pul s e d e t ec t e d. 0 = not detected. - 1 cs t r i p e r 1 = m acr ov i s i on c ol or s t r i p e pr o t ect i on b ur s t d et ec t e d. 0 = not detected. - 0 ct y p e r t hi s bi t i s v al i d o nl y w hen c ol or st r i p e pr ot ec t i o n i s d et e c t ed, i . e. c s t r i p e = 1. 1 = ty p e 2 c ol or s t r i pe pr ot e c t i o n 0 = type 3 color stripe protection - 0x031 ? chip status ii (cstatus2) bit function r/w description reset 7 vc r r v c r si gn al i n di c at or - 6 w k a i r r w e ak si gn al i n di c at or 2 - 5 w k a i r 1 r w e ak si gn al i n di c at or 1 - 4 vs t d r s t a nd ar d l i n e p er f i el d i n di c at or - 3 ni n t l r n o n- i nt er l ac e d s i g nal i ndi c a t or - 2 w s sdet r 1 = w s s da t a de t e ct ed . 0 = not d e t e c ted . - 1 e d sdet r 1 = ed s da t a de t ec t ed . 0 = not d e t e c ted . - 0 cc de t r 1 = c c d a t a det ec t e d. 0 = n o t det ec t e d. - 0x032 ? h monitor (hfref) bit function r/w description reset 7 - 0 h f r e f, e t c . r ho ri zon t a l l i n e fr equen cy i n d i ca t o r hr ef[ 9 :2 ] / g val[8 : 1 ] / ph errd o / cg ai n o / b a mp o / m i n a v g / sy t h rd / s y a m p - 0x033 ? clamp mode(clmd) bit function r/w description reset 7 - 6 fr m r / w fr ee run m o d e . 0 x = au t o m o d e 10 = 6 0 h z 11 = 5 0 hz 0h 5- 4 y nr r/ w y hf n oi s e r e d uc t i o n. 0 = no ne 1 = sm a l l e st 2 = s m a l l 3 = m e d i um 0h 3- 2 clm d r/ w cl a m pi ng mod e c o nt r ol . 00 = s y n c top 1 = a u to 2 = p e d e s t a l 3 = n/a 1h 1 - 0 p s p r / w sli c e l e v e l . 0 = l o w 1 = m e d i um 2 = h i gh 1h
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 59 r ev. a 0 2 /05 /20 08 0x034 ? id detection control (nsen/ssen/psen/wkth) bit function r/w description reset 7- 6 i nd ex r/ w these two bits indicate which of the four lower 6-bit registers is currently being controlled. t h e w r i t e s e q ue n c e i s a tw o s t e ps pr o c es s u nl e ss t h e s a me r egi st er i s w r i t t e n. a w r i t e o f { i d , 0 0000 0 } se l e ct s one o f t h e f o u r r e g i st e r s t o be w r i tten . a s u bsequen t w r i t e w ill a ct u a l l y w r i t e i n to t he reg i s t e r. 00 5 - 0 n s e n / s sen / p sen / wk t h r / w id x = 0 contro l s t h e n t sc i d d e t ec ti on sen s i t iv i t y ( n s e n ). id x = 1 contro l s t h e sec am id de t e ction sen siti v ity (s se n ). id x = 2 contro l s t h e pal i d de t e ction sen siti v ity (ps e n ). id x = 3 contro l s t h e w e ak si gna l de t e c t i o n s e n s iti v i t y (w k t h ) . 1 e / 20 / 1c / 2a 0x 035 ? clamp control (c l c n t l) bit function r/w description reset 7 ct es t r/ w cl a m pi ng c o nt r ol f or d eb u g us e. 0 6 y clen r/ w 1 = y channel clamp disabled 0 = enab led. 0 5 cc le n r/ w 1 = c channel clamp disabled 0 = enab led. 0 4 v c l e n r / w 1 = v c h anne l clam p d i sab l ed 0 = enab led. 0 3 gte s t r/ w 1 = t e st . 0 = no r m al ope r a t i on . 0 2 vl pf r/ w s y nc f i l t er b an dw i dt h c o nt r ol 0 1 ck ly r/ w cl a m pi ng c u r r e nt c o nt r ol 1. 0 0 ck l c r/ w cl a m pi ng c ur r e nt c o n t r ol 2. 0 0x 038 ? anti- a l iasi ng fil t er a nd d ecod er contro l bit function r/w description re set 7 d ec_ sel r / w ana l og adc i npu t se lection 0 : i nput fr om r g b p a t h 1 : input from decoder path 1 6- 4 res er v e d r/ w reserved - 3 fbp y r/ w a nt i - a l i a s i n g fi l t er c ont r ol c h a n nel y 0 : fil te r 1 : b y p a ss 0 2 fbp v r/ w a nt i - a l i a s i n g fi l t er c ont r ol c h a n nel v 0 : fil te r 1 : b y p a ss 0 1 fbp c r/ w a nt i - a l i a s i n g fi l t er c ont r ol c h a n nel c 0 : fil te r 1 : b y p a ss 0 0 m i x ( s y+ c ) r / w a n a l o g yo u t co n t r o l 0 : y o u t pu t, 1 : y + c ou t p u t 0 del e t e d : v del e t e d : v
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 60 r ev. a 0 2 /05 /20 08 fl a t pa n el di sp l a y re gi s t er s 0x040 to 0x04f ? scaler input control registers address bit r/w description reset 7 r/ w t hi s bi t h as d u al f u n c t i on. i t s er v es a s o d d f i el d det e c t i o n me t h od s el e ct i on or i t u 6 5 6 p r og r e ss i v e / i n te r l aced se l e c t i o n . i f b i ts 3 : 2 o f inde x 44h does no t choo s e i t u 656 : od d f i el d d et ect i on m et ho d f or di gi t al i n pu t p or t 0: u s e i nt er n al def a ul t me t ho d 1: u s e d et ec t i o n met h o d de f i ne d b y r egi st er 0x 45 if b i t s 3 : 2 s e l e c t s i t u 656 , t h is b i t se t s the i n p u t t o i n t e rl aced ( 0 ) o r p r og r e s s i v e ( 1 ). 0 6 r/w invert internal detected field signal 0 5 r/ w f i el d is det er mi ned by the l eading or trai l i n g edge of i n put v s y nc w hen using 0x 45 for fi el d d e t e r m i na ti o n . 1 : t r a i li n g e dge. 0 4 r/w enable csync (composite sync); dtvhs is treated as a csync input. 0 3 r/w de polarity of the digital source. 0: active high 0 2 r/w hsync polarity of the digital source. 0: active high 0 1 r/w vsync polarity of the digital source. 0: active high 0 0x 0 4 0 0 r/ w i nv er t di gi t al i n put p or t d t v clk pol ar i t y , 0: ri s i n g ed g e 1: f al l i n g e dg e 0 address bit r/w description reset 7 r/ w 0= c o a s t si g n a l st ay s at ei t h er 0 or 1. 1 = enab le co ast si gna l ou t p u t. 0 6 r/ w chan ge c o a s t p o l a r i ty i n t h e d i s abl e d st at e an d def aul t st a t e. 0 : coa s t i s def a ul t ed t o ? 0 ? a nd dr i v en t o ? 0 ? ou t s i de of t he w i ndow def i ned by 0 x 44 1 : coa s t i s def a ul t ed t o ? 1 ? a nd dr i v en t o ? 1 ? ou t s i de of t he w i ndow def i ned by 0 x 44 0 5 r/ w s e l e ct e x p l i c i t d e ( da t a enab l e a l s o ca ll ed h a f o r ho ri z o n t a l a ctiv e ) ; 0: ha i s as s er t e d i n t he i np ut a c t i v e r e gi o n d ef i n e d by re gi s t er s 0x 47 t hr o u gh 0x 4 d 1: ha i s def i n e d b y i ndi v i du al v i de o s o ur c e 1 4 r/ w 0 = pi n d t v de i s u s ed as t h e d at a e n abl e ( d e) . 1 = pi n d t v de i s u s ed as hs y n c i n p ut 0 3 r/ w res er v ed. 0 0 x 04 1 2 - 0 r/ w in pu t cl o ck dt vcl k del a y ti m e s e l e c t i o n . 000: n o del ay t i me i n s er t e d. e ac h i n c r e m e n t i nc r e as e s t h e del ay by 1 n s . 0 00
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 61 r ev. a 0 2 /05 /20 08 address bit r/w description reset 7 r/w enable field detection for digital input port when index 44 bit 1 & 0 is 2?b01. 0 6 r/w set this bit to ?1? if the dtvvs input is not a pulse but a ?field? signal. 0 5 r/ w i t u 65 6 ev e n f i el d v sy nc d el ay . 1: d el ay t h e as s er t i on t o t h e f al l i n g e dg e of ? h a? . 0: n o d el ay 0 4 r/ w u se fil t e r ed h s y n c t o m a i n ta i n cons t a n t input h s y n c pe ri o d . 0 3 r/w set this bit to 1 in 8 bit 601 mode if the cr data arrives before cb data. 0 0x 0 4 2 2 ?0 r/ w dat a b u s r o ut i ng s el ect i on f or di gi t al i n p ut por t fo r 24 b i t y p b p r o r 24 b i t r g b d t vd [2 3 : 1 6 ] d t vd [1 5 : 8 ] d t vd [7 :0 ] 0 0 0 : pr/b y /r pb /g 0 0 1 : pr/b pb /g y /r 0 1 0 : pb /g y /r p r /b 0 1 1 : pb /g p r /b y /r 1 0 0 : y/ r pb /g p r /b 1 0 1 : y/ r p r /b pb /g f or 1 6 bi t y pb/ p r : f ol l ow t he t a bl e a b o v e w i t h y an d p b. e x am p l e : if y d a t a is conn e c t e d t o dt vd [ 2 3 : 1 6 ] and pb /p r d a t a i s conne ct ed d tv d [ 7 :0 ], t h e bu s r o ut i n g s el ec t i o n s h o ul d b e s e t t o ? 1 01? . if e x p l ici t d e , i nde x 4 4 b i t [ 4 ], is se t, th e v e ry fi rs t d t vd e i s a ssum e d t o ha v e p b data . on t h e o t he r hand if ex p l i c i t d e i s rese t, i nde x 4 0 b i t [3 ] is u s ed t o se l e c t t h e o r d e r o f p b /p r. f or 8 bi t y / p b/ p r : f ol l ow t he t a bl e a bov e w i t h pr . e x am p l e : if y / pb / p r d a t a i s conne ct e d t o dt vd [ 1 5 : 8], th e bus r o u t i n g sel e c t i o n c a n be se t to ? 011 ? o r ? 101 ?. us e t he t a bl e b el ow f or t h e c or r e c t dat a or d er . in de x 41 b i t 5 i nde x 40 b i t 3 i n d e x 4 2 b i t 3 dat a o r de r 1 x 0 p b -y - p r- y 1 x 1 pr- y -pb - y 0 0 0 pb -y - p r- y 0 0 1 p r -y -pb - y 0 1 0 y -pb - y -p r 0 1 1 y -pr- y - p b 1 00 address bit r/w description reset 7 r/w when this bit is set to one, irq output is used to output the pllck. 0 6 r/w reserved. 0 5-4 r/w fpclk output driving capability control. 0 0 = rese rv e d 01 = 4m a 10 =8m a 11 = d i s a b l e d 10h 3 r/w when this bit is set to one, gpio[2] output is used to output the pllck. for pll operation monitoring. 0 2 r/w reserved. - 0x043 1-0 r/w dec_vs, dec_hs polarity control 0 0 = v s a c tiv e h i gn , h s a c ti v e lo w 01 = vs ac ti v e high , h s activ e h i g h 1 0 = v s a c tiv e low , h s ac ti v e l o w 11 = v s a c tiv e l o w , h s a c tiv e h i gh 10h
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 62 r ev. a 0 2 /05 /20 08 address bit r/w description reset 7 - 6 r / w p i n c o a s t is d r iv e n t o ? enab l e d ? sta t e i n the w i n d o w de fi n e d be l o w 00 : co ast enab l e d 1 h s y n c p e r iod be fo r e vs y n c and 7 hsy n c p e r iods a f t e r vs y nc 01 : co ast enab l e d 2 h s y n c p e r iods be f o r e v s y n c an d 8 hs y n c pe ri od s a f te r v s y n c 10 : co ast enab l e d 3 h s y n c p e r iods be f o r e v s y n c an d 9 hs y n c pe ri od s a f te r v s y n c 11 : co ast enab l e d 4 h s y n c p e r iods be f o r e v s y n c an d10 h s y n c pe riods a f te r v s y n c 00 5 r/w reserved 0 4 r/ w 1 : 8 b i t 6 0 1 i n pu t m o de 0 : 8b i t 6 56 i n pu t m o de 0 3 - 2 r / w i n p u t fo rm a t se le c t io n ; 00: 4 2 2 ( 1 6 b i t i t u 6 01) , 01: itu656 (8 bits) or itu601 (8 bit) ; determined by bit 4. 10 : 444, 1 1 : rg b 10 0 x 04 4 1 - 0 r / w in pu t video/dtv so u r c e se l e cti o n ; 00: i n t er n al a n al o g v i deo d e c o d er , 0 1 / 10 : dt v i n p u t port, 11: li ne l o c k a d c i n p ut por t . 00 add r ess bit r/w description reset 7 - 4 r/w horizontal ending locations of internal odd field detection for digital input port 0101 hor i zontal starting locations of internal odd field detection for digital input port 0x04 5 3 - 0 r / w s t a r t p i x e l en d pix e l s t a r t pi x e l e nd pix e l 000 0 32 64 1000 5 12 1024 000 1 64 12 8 1001 5 76 1152 001 0 12 8 25 6 1010 6 40 1280 001 1 19 2 38 4 1011 7 04 1408 010 0 25 6 51 2 1100 7 68 1536 010 1 32 0 64 0 1101 8 32 1664 011 0 38 4 76 8 1110 8 96 1792 011 1 44 8 89 6 1111 9 60 1920 0100 del e t e d : 0 1 = 444, ?
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 63 r ev. a 0 2 /05 /20 08 address bit r/w description reset 0 x 04 6 7 - 0 r/ w o ffse t a m ount t o r e -cons tr u ct v s y n c fr om c s y n c i npu t. the l t o h tr ans i t ion o f c s y nc i npu t pr ov i des t h e l t o h t r a nsi t i o n of hs y nc. t hi s r e gi s t er d ef i n es t h e a m o u nt of o f f s et f r o m t hi s t r a nsi t i o n e dg e f or g e ner at i n g vs y nc. 0010 0000 address bit r/w description reset 0x047 7 - 0 r/w input active window definition: horizontal starting pixel position - low byte. 0000 0000 address bit r/w description reset 0 x 04 8 7 - 0 r/ w in pu t ac ti v e w i n d o w d e f i n i ti on : hor i z ont al e n di n g pi x el po si t i on - l o w b y t e 1100 1111 address bit r/w description reset 7 - 4 r/ w in pu t ac ti v e w i n d o w d e fi n i ti on : hor i z ont al e n di n g pi x el po si t i on ? hi g h ( t ot al 1 2 bi t s ) . t hi s pos i t i o n i s r ef e r enc ed t o t h e r i s i ng e d ge o f i np ut h sy nc. 0010 3 r/w reserved. - 0 x 04 9 2 - 0 r/w input active window definition: h o r i z o n t a l s t a rti n g pix e l pos i tion - h i gh ( t o t a l 11 b i ts ) t hi s pos i t i o n i s r ef e r enc ed t o t h e r i s i ng e d ge o f i np ut h s y nc. 000 *note: the value written in this register does not come into effect until a register write to index 0x047 or 0x048 is followed. address bit r/w description reset 0x 0 4 a 7 - 0 r / w in pu t ac ti v e w i n d o w d e fi n i ti on : od d f i el d v er t i c al li ne s t ar t p o s i t i o n - low by t e 0001 0011 address bit r/w description reset 0x 0 4 b 7 - 0 r / w in pu t ac ti v e w i n d o w d e fi n i ti on : ev en fi el d v e r t i c al li ne s t ar t p o si t i on - l ow b y t e 0001 0011 address bit r/w description reset 0x04c 7-0 r/w input active window definition: vertical length - low byte 0000 0000 address bit r/w description reset 7 r/w reserved. 0 6 - 4 r / w in pu t ac ti v e w i n d o w d e fi n i ti on : v e rti ca l l eng t h - h i gh (to t a l 1 1 b i ts)* th e un i t o f t h i s l e ng t h i s on e i n p u t hs y n c . 011 3 - 2 r / w in pu t ac ti v e w i n d o w d e fi n i ti on : ev en fi el d v e r t i c al li ne s t ar t p o si t i on - hi g h ( t ot al 1 0 bi t s ) * . t hi s pos i t i o n i s r ef e r enc ed t o t h e r i s i ng e d ge o f i np ut v sy nc. 00 0x 0 4d 1 - 0 r / w in pu t ac ti v e w i n d o w d e fi n i ti on : o d d fi e l d v e rti ca l l i n e st a rt positi on - h i gh (to t a l 10 bits)* . t hi s pos i t i o n i s r ef e r enc ed t o t h e r i s i ng e d ge o f v sy nc. 00 *note: when the explicit-de is not used (register 0x041, bit 5), the input active window is defined by the above h-active and v -active registers. deleted: i
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 64 r ev. a 0 2 /05 /20 08 address bit r/w description reset 7 r/w reserved. 0 6 r/ w gpi o [2] i n p u t/ ou t put s e l e ct i on. 1 : o u t put ( s ee 0 x 4 3 an d 0x 50 f o r dat a s our c e ) . 0: i n p ut 0 5 r/ w gpi o [1] i n p u t/ ou t put s e l e ct i on. 1 : ou t p u t (se e 0x 4 f fo r da ta so u r c e ). 0 : i n pu t 0 4 r/ w gpi o [0] i n p u t/ ou t put s e l e ct i on. 1 : ou t p u t (se e 0x 4 f fo r da ta so u r c e ). 0 : i n pu t 0 3 r/w reserved - 2 r/w reserved. - 1 r/w reserved. - 0x 0 4 e 0 r/w reserved. - address bit r/w description reset 7 r/w invert pin gpio[1] output. 0 6 - 5 r/ w ou t put s our c e s el e c t i o n f or pi n gp i o [ 1] . 0 0 : dat a w r itte n t o b i t 4, 01: vdlo ss, 10 : hloc k , 11 : b w _a c tiv e 00 4 r/w read: s how s t h e sampl ed i np ut v al u e of pi n gpi o [ 1 ] w r i t e: ho l ds t he d at a th at c a n be out put t o pi n gpi o [ 1] 0 3 r/ w i n v e rt p i n g p io [0 ] o u tpu t. 0 2 - 1 r/ w ou t put s our c e s e l ect i o n f or pi n gp io[ 0] . 00: d at a written to bit 0, 01: field, 10: hz50, 11: slock 00 0x 0 4 f 0 r/w read: s how s t h e sampl ed i np ut v al u e f r om pi n gp io[ 0] w r i t e: ho l ds t he d at a th at c a n be out put t o pi n gpi o [ 0] 0 add r e s s bit r/w description reset 7 - 3 r/w reserved. - 2 r/ w i nvert pin gpio[2] output. 0 1 r/ w ou t put s our c e s e l ect i o n f or pi n gp io[ 2] . 0 : d a t a w r i t ten to b i t 0 1 : s s -p l l c l o ck ou tpu t if p l l tes t m o d e se t(reg f e [ 2 ] ). 0 0 x 05 0 0 r/ w read: s how s t h e sampl ed i np ut v al u e f r om pi n gpio[ 2] w r i t e: ho l ds t he d at a th at c a n be out put t o pi n gpi o [ 2] 0
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 65 r ev. a 0 2 /05 /20 08 0x051 to 0x05c ? input format measurement registers address bit r/w description reset 0x 0 5 1 7- 0 r/ w i np ut m e as ur eme nt w i n d ow def i n i t i on: h o r i z o n t a l s t a rt - lo w b y te 0010 0000 address bit r/w description reset 0x 0 5 2 7- 0 r/ w i np ut m e as ur eme nt w i n d ow def i n i t i on: h o r i z o n t a l s t op - lo w b y te 1111 1111 address bit r/w description reset 7- 4 r/ w i np ut m e as ur eme nt w i n d ow def i n i t i on: h o r i z o n t a l s t op - h i gh t h r e e b i ts ( t ota l 12 b i ts) th is h o r i zon t a l s t op p o siti on i f r e f e r enced t o the ri s i ng edge o f i n p u t hsy n c a n d t h e un i t is o n e inpu t p i x e l . 0001 3 r/w reserved 0 0x 0 5 3 2- 0 r/ w i np ut m e as ur eme nt w i n d ow def i n i t i on: hor i z ont al st ar t - hi g h t hr ee bi t s ( t o t al 1 1 bi t s ) th is h o r i zon t a l s t a rt pos i t ion i f r e f e r e nced t o t h e ri s i ng edg e o f inpu t hsy n c and the un it i s one inpu t p i x e l . 000 address bit r/w description reset 0x 0 5 4 7- 0 r/ w i np ut m e as ur eme nt w i n d ow def i n i t i on: v e rti ca l s t a rt - l o w b y te 0010 0000 address bit r/w description reset 0x 0 5 5 7- 0 r/ w i np ut m e as ur eme nt w i n d ow def i n i t i on: v e rti ca l s t op - low b y te 1111 1010 address bit r/w description reset 7 r/w reserved 0 6- 4 r/ w i np ut m e as ur eme nt w i n d ow def i n i t i on: v e rti ca l s t op - h i gh t h r e e b i ts (to t a l 11 b i ts) th is ve rti ca l s t op p o siti on is r e f e r e n c e d t o t h e ri s i n g edg e o f i n pu t v sync an d t h e un it i s one i npu t hsy nc. 000 3 reserved 0 0x 0 5 6 2- 0 r/ w i np ut m e as ur eme nt w i n d ow def i n i t i on: ver t i c al st ar t - hi g h t hr ee bi t s ( t o t al 11 bi t s ) th is ve rti ca l s t a rt pos i t ion i s r e f e r enced t o t h e r i si ng e dge o f i npu t vsync and t h e un i t is o n e i n pu t hsy nc. 000 address bit r/w description reset 0x 0 5 7 7- 0 r res ul t 0: d at a by te 0 of 4 by t es m ea s ur eme nt r es ul t ( 0x 5b bi t s 7- 4 s pe c i f i es w hi c h r es ul t t o r e a d out ) - address bit r/w description reset 0x 0 5 8 7- 0 r res ul t 1: d a t a by te 1 of 4 by t es m ea s ur eme nt r es ul t (0 x 5 b b i ts 7 - 4 specifi e s w h ich r e s u lt to r ead ou t) - address bit r/w description reset 0x 0 5 9 7- 0 r res ul t 2: d a t a by te 2 of 4 by t es m ea s ur eme nt r es ul t (0 x 5 b b i ts 7 - 4 specifi e s w h ich r e s u lt to r ead ou t) - address bit r/w description reset 0x 0 5 a 7- 0 r res ul t 3: d at a by te 3 of 4 by t es m ea s ur eme nt r es ul t (0 x 5 b b i ts 7 - 4 specifi e s w h ich r e s u lt to r ead ou t) -
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 66 r ev. a 0 2 /05 /20 08 address bit r/w description reset 7 - 4 r/ w sel e c t w hi c h me a s ur eme n t r es ul t t o r ea d o ut f r o m 0x 5 7 ~ 0x 5a 0 0 00: p has e m eas ur e m e n t r e s ul t - b l ue ( us e re s ul t 3 - 0 r e gi s t er s) 0 0 01: p has e m eas ur e m e n t r e s ul t - g r e e n ( us e res ul t 3- 0 r e gi s t er s ) 0 0 10: p has e m eas ur e m e n t r e s ul t - r e d ( us e r e s ul t 3 - 0 r egi st er s) 0 0 11: m i ni mu m v al u e ( r e s ul t 2: r, r es ul t 1: g , res ul t 0: b ) 0 1 00: m a x i mu m v al u e ( r e s ul t 2: r, r es ul t 1: g , r es ul t 0: b) 0 1 01: v sy nc p er i o d ( r e s ul t 3, 2) h sy nc p er i o d ( r e s ul t 1, 0) 0 1 10: hs y n c ri s e t o h sy nc f al l i nt er v al ( r es ul t 1, 0) an d hs y nc r i se t o hac t i ve fa l l in t e rv a l (resu l t 3 , 2 ) . 01 1 1: vs y nc pul s e w i dt h ( r e s ul t 1 , 0) , hor i z o nt al pi x el c o u nt er v al u e at t h e l e a d i n g edge o f vs y n c ( r e s u l t 3 , 2 ). 10 00 : m i n ho riz o n t a l activ e sta rti n g pi x e l (re s u l ts 1 & 0 ) m a x h o riz o nta l activ e sta rti n g pi x e l (re s u l ts 3 & 2 ) 1 00 1: m i n h or i z o nt al a c t i v e e n di n g pi x el ( r es ul t s 1 & 0) m a x h o riz o nta l activ e end i ng pix e l ( r e s u l ts 3 & 2 ) 10 10 : ve r t ica l ac ti v e s t a rti ng l i ne r e c o rded w i th a. m i n ver t i c a l a c t i v e st ar t i n g li ne ( re s ul t s 1 & 0) b. m a x v er t i cal ac t i v e st ar t i ng li n e ( r e s ul t s 3 & 2) 10 11 : ve r t ica l ac t i v e e n d i ng l i ne r e co r d ed w i th a. m i n ver t i c a l a c t i v e en di n g li n e ( r es ul t s 1 & 0) b. m a x v er t i cal ac t i v e e n di n g li n e ( r es ul t s 3 & 2) 1 10 0: h or i z o nt a l c o u nt e r v al u e w hen b uf f er r e a d poi nt er s t ar t s t o t o g gl e. ( r e s u l ts 1 & 0 ) 1101 : l u m i nance v a lu es. m i n i m u m l u m i na n c e ( r es u l t 0) m a x i m u m l u m i n a n c e ( r esu l t 1) a v er a ge l u m i n anc e ( r e s ul t 2) 1110 : v s y n c peri o d m easu r ed w i t h 2 7 m h z cl oc k ( r e s u l t 2 , 1 & 0 ) . 0000 3 - 2 r/ w fi el d s el ec t i o n f or i n p ut m e a s ur e m e nt 00: o d d f i el d o nl y 0 1: ev e n f i el d o nl y 1x : di s r e g ar d f i el d 00 1 r/ w r e s e rv ed . 0 0x 0 5 b 0 r/ w s t a rt i nput m e a su r em e n t. th i s b i t is s e lf- c l e a r e d a f t e r t h e m easur em e n t i s do ne . 0 address bit r/w description reset 7 r/ w 0 : us e fpcl k f o r i n pu t h s y n c p e r i o d m easur em ent. 1: u s e 2 7m h z cl oc k f or i n put hs y nc per i o d m e a s ur e m e nt . 0 6 - 4 r/ w noi s e ma s k bi t s f o r e ac h of t he 3 l s b i n p ut s i gn al s . 000 3 - 1 r/ w e r r o r to l e r a n c e be f o r e a sse rti ng "chan ge de t e ct e d " s t a t us 0 0 0 : ex a c t m a t c h 0 01: u p t o 4 coun t s 0 10 : up t o 8 c o un ts 011 : up to 16 coun ts 10 0 : up t o 32 counts 101: up to 64 counts 110: up to 128 counts 111: up to 256 counts. 0 00 0x 0 5c 0 r/ w e nab l e i np u t vs y n c , h s y n c pe ri od chan ge / los s de t ec t i on . w h en t h i s b i t is set, the i n t e r n a l circ uitry w i l l p e r f o r m new m easu r em ents. the ne w re su lt s ar e c o m p ar e d ag ai n s t t h e r e s ul t s r et ai n e d i n t h e r e gi s t er s o bt ai n ed by t h e mo s t r ec e nt me a s ur e m en t . 0 address bit r/w description reset 7 - 4 r/ w th r e sho l d v a l u e for i npu t a ctiv e reg i on d e t ec ti on . ea c h i ncr e m en t i nc r e a s es t h e t hr es h ol d v al u e by 16. 0011 3 r/ w 1 : enab l e l um i nanc e m easu r em e nt . 0 2 - 1 r/ w n o i se fi lt e r se l e cti o n f o r l u m i nance m easu r e m en t. 00 0x 0 5d 0 r/ w r e s e rv ed . 0
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 67 r ev. a 0 2 /05 /20 08 0x060 to 0x06b ? zoom control registers address bit r/w description reset 0x 0 6 0 7 - 0 r/ w hor i z ont al ( x - d i r e c t i o n) s c al e u p f a ct or ? hi gh er fr a c t i o n b y t e ( c oar s e a dj ust me n t ) 6 5536 * ( i npu t ho r i zon t a l activ e pix e l num b er) / (f l a t pane l ho ri zon t a l activ e p i x e l n u m ber) e x am p l e : vga 640 x 4 80 , p a ne l r e so l u ti on : 10 24 x 768 6 5536 * 640 / 1 024 = 409 60 = 0a 0 00h e x am p l e : de code r 7 2 0 x 240 , pane l re so l u ti on : 1024 x 7 6 8 6 5536 * 720 / 1 024 = 460 80 = 0b 4 00h 1011 0100 address bit r/w description reset 0x 0 6 1 7 - 0 r/ w h o r i z o n t a l (x- d irection ) s ca l e do w n fa c t o r - fr a c ti on by te 1 2 8 * (i np u t ho ri zon t a l a c ti v e p i x e l nu m ber) / ( f l a t p ane l ho ri zon t a l ac ti v e p i x e l nu m ber) e x am p l e : de code r 7 2 0 x 240 , pane l re so l u ti on : 640 x 480 1 2 8 * 7 2 0 / 640 = 1 4 4 = 090h 1000 0000 address bit r/w description reset 0x 0 6 2 7 - 0 r/ w ver t i c al ( y - d i r ec t i o n) s c al e u p f a ct or ? hi gh er f r ac t i on b y t e ( c o ar s e a dj us t me n t ) 6 5536 * ( i npu t ve r t i ca l activ e p i x e l n u m b e r ) / ( f l a t pane l ve r t ic a l ac ti v e p i x e l n u m b e r ) e x am p l e : vga 640 x 4 80 , p a ne l r e so l u ti on : 10 24 x 768 6 5536 * 480 / 7 6 8 = 40960 = 0 a 00 0h e x am p l e : de code r 7 2 0 x 240 , pane l re so l u ti on : 1024 x 7 6 8 6 5536 * 240 / 7 6 8 = 20480 = 0 5000h 0101 0000 address bit r/w description reset 7 r/w 1: enable panorama / water-glass scaling. 0 6 - 5 r/w reserved. 00 4 r/ w s e t zoom b y - p a s s. w hen th i s b i t is se t, t h e ho ri z ont a l and ve rti ca l s c a l e u p f a cto r s has no e f f e cts . 0 3 - 2 r/ w in tege r po rti o n o f v e r t ic a l (y -d ir e c ti on ) sca l e f a c t o r ( t o t a l 1 8 b i ts ). fo r v e rtica l s c a l e up , m a x i m u m v al ue i s 0x 1 0 0 00. f or v er t i c al y - di r ect i o n s c al e d ow n , t he v al u e s h oul d be l ar ger t ha n 0x 10 0. v er t i c al s c al e f a c t or < 0x 1 0 0 00 : u p sc al i ng v er t i c al s c al e f a c t or = 0x 1 0 0 00 : n o sc al i ng v er t i c al s c al e f a c t or > 0x 1 0 0 00 : d ow n s c al i n g t he max v er t i c al d ow n s c al i n g f ac t or t h at t h e s c al er c an h a ndl e i s 0x 2 00 0 0. 00 1 r/w horizontal (x-direction) scale down factor ? integer portion bit (total of 9 bits) 0 0x 0 6 3 0 r/w horizontal (x-direction) scale up factor ? integer portion bit (total 17 bits) 0 address bit r/w description reset 0x 0 6 4 7 - 0 r/ w hor i z ont al ( x - di r e c t i o n) s c al e u p of f s et t hi s of f s et i s us ed t o a dj u st t h e i ni t i al v al ue f or t he x - di r ect i on s c al e u p op er at i on. 0000 0000 address bit r/w description reset 0x 0 6 5 7 - 0 r/ w ver t i c al ( y - di r ec t i o n) s c al e u p of f s e t f or o dd f i el d t hi s of f s et i s us ed t o a dj u st t h e i ni t i al v al ue f or t he y - dir ect i on s c al e u p op er at i on. 1000 0000 address bit r/w description reset 0x 0 6 6 7 - 0 r/ w hor i z ont al no n- di s pl ay pi x el n umb e r a ppl i e d t o bot h l ef t a n d r i ght s i d e s . t hi s i s u s ef ul w he n d i sp l a y i n g 4 : 3 i m a g e on w i d e s cr e e n 16 : 9 p ane l. ex a m p l e : a w i d e sc r een p ane l w i th 1024 h o r iz o n t a l p i x e l s . if th i s reg i st e r has a v a l u e of 10 0 , t he ac ti v e ho riz o n t a l d i s p l a y w ill b e 824 p i x e l s . e a ch si de is ? b l a c k ed ? out b y 1 0 0 p i x e ls. t hi s r e gi s t er al s o s er v es a s t he p a nor ama hor i z ont al w i dt h d ef i ni t i on. 0000 0000 address bit r/w description reset 7 r/ w 1 : non - d i sp l a y l e ft/ri g h t inde pende nt con tro l .. use 0 x 66 ,67 [ 1 : 0 ] on l y fo r l e ft a n d use 0 x 6c ,67[5 : 4 ] fo r ri gh t, 0 : u s e 0 x 66 , 6 7 [ 1 : 0] f o r bo t h l e ft a n d r i gh t. 0 5 - 4 r/w thnd2[9:8] non display width for right side (msb) 00 3 - 2 r/w reserved - 0x 0 6 7 1 - 0 r/w high 2 bits of 0x066 register. 00
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 68 r ev. a 0 2 /05 /20 08 address bit r/w description reset 0x 0 6 8 7 - 0 r/ w hor i z ont al s c al e at t h e si d e of di s pl ay i n p a nor a m a s c al i n g mod e . 0000 0000 address bit r/w description reset 0 x 06 9 7 - 0 r/ w hor i z ont al ( x - d i r e c t i o n) s c al e u p f a ct or ? l ow er f r a c t i on b y t e ( f i n e adj us t m e n t ) 0000 0000 address bit r/w description reset 0x 0 6 a 7 - 0 r/ w ver t i c al ( y - d i r ec t i o n) s c al e u p f a ct or ? l ow er fr a c t i o n by t e ( f i n e a d j u s t m e nt ) 0000 0000 address bit r/w description reset 0x 0 6 b 7 - 0 r / w v e rti ca l (y - d ire ction ) sca l e up o f f s e t fo r e v en fi e l d 0000 0000 address bit r/w description reset 0x 0 6 c 7 - 0 r / w th nd2 [ 7 : 0 ] non d i sp l a y w i d t h f o r r i gh t s i de ( l s b ) 0000 0000 address bit r/w description reset 7 - 6 r/ w res er v e d - 0x 0 6 d 5 - 0 r/ w t op ( or bot h t o p an d b ot t o m ) l i n e nu mb er t o b e mas k e d 00 0000 address bit r/w description reset 7 r/ w 1 : t o p / b o tt om m a s ki n g i n depe ndent c o n t r o l ena b l e . ( 0 x 6 e [ 5 : 0 ] i s ac ti v e and 0 x 6d on ly con t r o ls to p ) , 0 : 0 x 6d c o ntro l s bo t h t o p and bo tt om [def au lt] 0 6 r/ w res er v e d - 0x 0 6 e 5 - 0 r / w b o tt o m l i ne num b e r t o be m a sked. 00 0000
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 69 r ev. a 0 2 /05 /20 08 0x070 to 0x07b ? image adjustment registers address bit r/w description reset 7 r/ w re se rv ed . 0 6 r/ w t h er e ar e 2 s et s o f r e gi s t e r s f or i n de x 71 ~ 76. 0: s el e c t t he 1 st s et , r / g / b c o n t r as t a nd r b r i g ht n es s 1: s el e c t t he 2 nd s et , y / c b/ c r c on t r as t an d y b r i ght ne s s 0 0 x 07 0 5 - 0 r/ w h ue a dj us t me nt f or di gi t al i np ut p o r t . t he s e bi t s c ont r ol t h e c ol or hu e. t h e r a ng e i s + 4 5 d egr ees t o ?4 5 d egr ee s i n 1. 4 d e gr e e i nc r em e nt s . 0 d e g r ees i s t h e de fau l t (xx 1 0 0000 ) 10 0000 address bit r/w description reset 0x 0 7 1 7 - 0 r/ w r e d (o r y) c o n t ra s t ad ju s t m e n t fo r a l l in p u t so u r c e s 80 h + : h i ghe r con t ra s t , 80h : neu t r a l , 80h -: lo w e r con tras t 1000 0000 address bit r/w description reset 0x 0 7 2 7 - 0 r/ w g r een ( o r cb) con t r a st ad j u s t m e nt for al l i n pu t sour c e s 80 h + : h i ghe r con t ra s t , 80h : neu t r a l , 80h -: lo w e r con tras t 1000 0000 add r e ss bit r/w description reset 0x 0 7 3 7 - 0 r/ w blue ( o r c r) con t r a s t a d j u stm ent f o r a l l inpu t s o u r ces 80 h + : h i ghe r con t ra s t , 80h : neu t r a l , 80h -: lo w e r con tras t 10 00 00 00 add r e ss bit r/w descr i pt i on reset 0x 0 7 4 7 - 0 r/ w red (o r y ) br i g h t nes s ad j u st m ent f o r a l l i n pu t sou r c e s 80 h + : h i ghe r br i g h t ne ss , 80h: neu t r a l , 80 h -: low e r b r igh t nes s 10 00 00 00 add ress bit r/w descripti on reset 0x 0 7 5 7 - 0 r/ w green bright ne s s a d j ust men t f or al l i n put s our c e s 80 h + : h i ghe r br i g h t ne ss , 80h: neu t r a l , 80 h -: low e r b r igh t nes s 10 00 00 00 add r e s s bit r/w description reset 0x 0 7 6 7 - 0 r/ w blue brightne ss ad j u s t m e nt f o r a l l i n pu t sou r c e s 80 h + : h i ghe r br i g h t ne ss , 80h: neu t r a l , 80 h -: low e r b r igh t nes s 10 00 00 00 address bi t r/w description reset 7 - 4 r/ w c o r i n g function fo r p e a k i n g c o n t ro l. 0011 0x 0 7 7 3 - 0 r/ w p eak i ng ad j u st m e n t 1111 address bit r/ w d escription reset 7 r/ w s h a r pne ss f r e quenc y se lec t. 0 = low fre q . 1 = h i gh freq . 0 6 r/ w reserved. - 5 - 4 r/ w y nr. 00 0 x 07 8 3 - 0 r/ w s h arpness adjustment. 1010 address bit r/w d escription reset 7 - 4 r/ w re se rv ed . - 3 r/ w reserved. - 0 x 07 9 2 - 0 r/ w re se rved. - address bit r/w d escription reset 0x 0 7 a 7 - 0 r/ w re se rved. - address bit r/w d escription reset 7 - 4 r/ w re se rv ed . - 0x 0 7 b 3 - 0 r/ w re se rved 0100
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 70 r ev. a 0 2 /05 /20 08 0x 07c to 0 x 08b ? bl a ck / whi t e s t re tc h adjustment regi ste r s address bit r/w description reset 7 r/w 1: bw stretch test. 0 6 r/w 1: use histogram information. 0 5 r / w b l a ck l e v e l s e l e c t ion . 0 : 0 1 : 16 0 4 r/ w w h i t e l ev el s el e c t i o n. 0: 2 3 5 1: 2 5 5 1 3 r/ w bl ac k s t r et c h l i m i t . 1: s t r e t c h r eg ar dl es s of bl a c k l ev el , 0: li mi t st r et c h u p t o bl ac k l ev el 1 2 r/ w w h i t e s t r et c h l i m i t . 1: s t r e t c h r e g ar dl e s s of w hi t e l ev el , 0: li mi t s t r et c h u p t o w hi t e l ev el 1 1 r/ w 1: by p a s s b w st r et c h a n d pe a k i n g 0: n or m a l 0 0x 0 7 c 0 r/ w 1: b w s t r et c h e na bl e, 0: di s a bl e. 0 address bit r/w description reset 0x 0 7 d 7 - 0 r / w y m i n / m a x d e t ection w i n d o w sta rt l i ne , l o w e r 8 b i ts ( t o t a l 10 b i ts). 0000 1000 address bit r/w description reset 0x 0 7 e 7 - 0 r / w y m i n / m a x d e t ection w i n d o w l i n e end , l o w e r 8 b i ts ( t o t a l 10 b i ts). 1111 0110 address bit r/w description reset 7 - 4 r / w re se rv ed . 0000 3 - 2 r/ w y m i n/m ax det e c t i o n w i nd ow l i ne e n d, up p er 2 bi t s . 10 0x 0 7 f 1 - 0 r / w y m i n / m a x d e t ection w i n d o w sta rt l i ne , up pe r 2 b i ts. 00 address bit r/w description reset 0 x 08 0 7 - 0 r / w b w hd l y , y mi n / m a x d e t e cti on w i n d o w h m a r g i n fr o m s t a r t/end p i x e l o f h act ive. 0001 0000 address bit r/w description reset 7 - 6 r/ w r es er v e d 00 0 x 08 1 5 - 0 r/ w y m i n/m ax hor i z o nt al f i l t er g ai n. 00 1101 address bit r/w description reset 7 - 6 r/ w r es er v e d 00 0 x 08 2 5 - 0 r/ w y m i n/m ax ver t i c al f i l t er g ai n. 00 0011 address bit r/w description reset 0 x 08 3 7 - 0 r / w mi n i m u m r e qu i r ed y d i ffe r ence f o r b w str e tc h. if y m a x ? y m i n i s sm all e r than t h i s v a l u e , bw s tr e tc h w ill tu rned o ff. 0000 0000 address bit r/w description reset 0 x 08 4 7 - 0 r / w t i lt po i n t f o r b l a ck stretch . 0110 0111 address bit r/w description reset 0 x 08 5 7 - 0 r / w t i lt po i n t f o r w h ite stretch . 1001 0100 address bit r/w description reset 0 x 08 6 7 - 0 r / w m a xi m u m y m i n f o r bla c k str e t c h . if y m in i s b i g g e r t han t h is v a l u e , b l a ck str e tch w ill tu rned o ff. 0001 1000 address bit r/w description reset 0 x 08 7 7 - 0 r / w mi n i m u m y m a x for w h it e s t r e tc h . i f y m a x is sm a l l e r t h an t h i s v a l u e , w h i t e s t r e tc h w ill tu rned o ff. 1110 1000 address bit r/w description reset 7 r / w 1 : ad j u st w h it e s tre t ch ga i n f o r sm oothe r tr a n si e n t. 0: no ad j u st m ent. 1 6 r / w 1 : ad j u st b l a ck str e t ch ga in f o r s m oo th e r tr an s i en t. 0: n o ad j u st m ent. 1 5 r / w re se rv ed . 0 0 x 08 8 4 - 0 r / w am ou nt o f m o di fic a ti on f o r til t po i n t. 0 1010 address bit r/w description reset 7 r / w re se rv ed . 0 0 x 08 9 6 - 0 r/ w bl ac k / w h i t e s t r et c h fi el d r ec ur s i v e f i l t er gai n. 000 0010 address bit r/w description reset 7 - 5 r / w re se rv ed . 000 0x 0 8 a 4 - 0 r / w s t r e tc h o f f po i n t 0 1010
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 71 r ev. a 0 2 /05 /20 08 address bit r/w description reset 7 - 5 r/w reserved. 000 0x 0 8 b 4 - 0 r/w hysteresis for stretch on from stretch off state. 0 0100 0 x0 92 to 0x 09d ? osd co ntrol r eg i sters address bit r/w description reset 0x 0 9 2 3 - 0 r / w r e se r v e d fo r te s t . 0110 address bit r/w description reset 7 r / w fo n t r a m s e l e c t 0 : fon t r o m 1 : fon t r a m 0 6 r/ w 1: c h ar a c t er i t al i c ef f ec t e na bl e. 0 5 r / w 1 : cha r ac t e r under li n e effect enab l e . 0 4 r / w 1 : cha r ac t e r bo r d e r i n g/shado wi n g e f f e ct enab l e . 0 3 - 2 r/ w os d ra m aut o i n cr e a s e of w r i t e a d dr es s m od e s el ec t i o n. 0 0 : nor m al m o de 01 : fo n t dat a o r attri bu te a d d r e ss aut o m o d e 1 1 : font data aut o m ode(p r e v io us attri b u t e dat a aut o m ati c w r ite ) 00 1 r/ w os d ra m aut o c l e ar m ode 0 0x 0 9 4 0 r/ w font/o s d ram ser i al b u s a c c e ss 0: o s d ram 1: f ont ra m acc es s 0 address bi t r/w des c r i ption reset 7 r f or ev ery e n d of window 1 active, this signal is toggled. - 6 r f or ev ery e n d of active window, this signal is toggled. - 5 r/ w 1: e n a b l e character horizontal extension. 0 4 r / w r e g i s t e r 097h , 098h read m o d e s e l e c t i o n . 0 : no r m al d i sp l a y 1 : q v ga d i s p la y 0 0x095 3 - 0 r/ w res er v e d. 0000 address bi t r/w des c r i ption reset 0x 0 9 6 7 - 0 r/ w os d ra m addr e s s (word address for single byte access). 0000 0000 add r ess bi t r/w des c r i ption reset 0x 0 9 7 7 - 0 r / w o s d r a m data port hi (font data). - address bi t r/w des c r i ption reset 0x 0 9 8 7 - 0 r / w o s d r a m data port lo (font attribute). - address bi t r/w des c r i ption reset 0x 0 9 9 7 - 0 r/ w ser i al b us f o nt ram address. 0000 0000 add r ess bi t r/w des c r i ption reset 0x 0 9 a 7 - 0 r / w s e ri a l b u s font ram data port. - address bi t r/w des c r i ption reset 0x 0 9 b 7 - 0 r / w p r og r a mm abl e sram address start position for multi-color fonts. 0011 0001 add ress bi t r/w des c r i ption reset 7 r/ w w h e n s et , the content of osd ram bit16 is read out from bit 7 of index 094. 0 6 - 5 r/ w res er v e d. 000 4 r/ w os d o n/ o f f e nable control 0: osd on, 1: osd off 0 0x 0 9c 3 - 0 r / w c h a r a ct e r co l o r l ook up t a b l e wr ite add r e ss se l e ct. 0000 address bi t r/w des c r i ption reset 0x 0 9d 7 - 0 r / w c h a r a ct e r color look up table data port. 00h
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 72 r ev. a 0 2 /05 /20 08 0x 09 e to 0x 0ae ? osd wi n dow c o ntrol re gi sters address bit r/w description reset 7 - 4 r / w w i n d o w a l pha b l en d i n g c o l o r s e l e cti o n . 0000 3 - 2 r/ w res er v e d. 00 0x 0 9 e 1 - 0 r/ w w i nd ow s el e c t i o n ( w i n d ow #n) . 00 address bit r/w description reset 7 r / w o s d w i ndo w #n b a c k g r ou nd co l o r loo k- up tab l e se l e ction . 0 6 - 4 r / w o s d w i ndo w #n b a c k g r ou nd co l o r co ntro l ( r eg ist e r se tti n g fl o w fo r osd : s t ep_3 ) . 0 0 0 : blac k 0 0 1 : blue 01 0 : g r een 01 1 : c y an 1 0 0 : red 10 1 : m age n t a 110 : y e ll o w 111 : w h i t e 0 00 3 r/ w os d w i n d ow # n 3- d ef f e c t t o p/ b ot t om t o g g l e. 0 2 r / w o s d w i ndo w #n 3 - d e f f e ct enab l e . 0 1 r/ w os d w i n d ow # n 3- d ef f e c t l ev el c ont r ol . 0 0x 0 9 f 0 r / w o s d w i ndo w #n e nab l e . 0 address bit r/w description reset 7 - 6 r/ w res er v e d. 00 5 - 4 r/ w os d w i n d ow # n v- s t ar t l o c at i o n h i g h 2 bi t s ( t ot al 1 0 b i t s ) . 00 3 r/ w res er v e d. 0 0x 0 a 0 2 - 0 r/ w os d w i n d ow # n h- st ar t l o c at i on h i gh 3 bi t s ( t ot al 1 1 bi t s ) . 000 address bit r/w description reset 0x 0 a 1 7 - 0 r / w o s d w i ndo w #n h - s t a rt loca t i o n l o w 8 - b i t (1 p i x e ls pe r st ep ). 0000 0000 address bit r/w description reset 0 x 0a 2 7 - 0 r / w o s d w i ndo w #n v - sta rt loca t i o n lo w 8 - b i t (1 sc a n l i nes pe r st ep ) . 0000 0000 address bit r/w description reset 7 - 6 r/ w res er v e d. 00 0x 0 a 3 5 - 0 r/ w os d w i n d ow # n h- w i dt h ( 1 c h ar a c t er w i dt h p er s t e p ) . 00 0 0 00 address bit r/w description reset 7 - 6 r/ w res er v e d. 00 0x 0 a 4 5 - 0 r/ w os d w i n d ow # n v- h ei ght ( 1 c h ar a c t er h ei ght p er s t e p) . 00 0 0 00 address bit r/w description reset 7 r/ w os d w i n d ow # n bor d er c ol or e n abl e. 0 6 - 4 r/ w os d w i n d ow # n bor d er c ol or c o nt r ol . 000 0x 0 a 5 3 - 0 r / w o s d w i ndo w #n b o r d e r co l o r w i d t h ( 1 p i x e l o r s can l i n e pe r st ep ) . 0000 address bit r/w description reset 7 r / w o s d w i ndo w #n b o r d e r co l o r look-up tab l e se l e c t i o n bi t. 0 0x 0 a 6 6 - 0 r / w o s d w i ndo w #n h - bo r d e r w i dt h ( 1 p i x e l pe r s t ep ). 000 0 000 address bit r/w description reset 7 r/ w res er v e d 0 0x 0 a 7 6 - 0 r / w o s d w i ndo w #n v - bo r de r w i dth ( 1 scan l i ne pe r s t ep ) . 000 0 000 address bit r/w description reset 7 - 4 r / w c h a r a ct e r v - spa ce i n si de w i n d o w # n ( 1 scan li ne pe r st ep ). 0000 0x 0 a 8 3 - 0 r / w c h a r a ct e r h - space i n si de w i nd o w #n ( 1 p i x e l pe r s t ep ) 0000 address bit r/w description reset 7 - 6 r / w o s d w i ndo w #n v e rti ca l zo om . 00 : no zoom , 01 : x 2 , 10 : x 3 , 11 : x 4 00 5 - 4 r / w o s d w i ndo w #n h o r i z o n t a l zo o m . 0 0 : no zoom , 01: x2 , 10 : x 3 , 1 1 : x 4 00 0x 0 a 9 3 - 0 r/ w res er v e d. 0000 address bit r/w description reset 0x 0 a a 7 - 0 r / w o s d d i sp la y r a m sta rti n g add r e s s ( l o w b y te ) o f o s d w i ndo w # n . 0000 0000
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 73 r ev. a 0 2 /05 /20 08 address bit r/w description reset 7 r/ w osd window #n shadow enable. 0 6 - 4 r/ w osd window #n shadow color control. 000 0x 0 a b 3 - 0 r / w osd window #n shadow width. 0000 address bit r/w description reset 7 - 4 r/ w reserved. 0000 0x 0 a c 3 - 0 r / w o s d w i ndo w #n a l ph a b l en d i n g amo un t. 0000 address bit r/w description reset 7 r / w o s d w i ndo w #n sha d o w c o lo r look -up tab l e se l e c t i o n . 0 6 r / w 1 : osd w i nd o w #n m u lti co l o r f o n t enab l e . 0 5 r/ w 1: c h ar a c t er v er t i c al ex t en s i o n en a bl e. 0 4 r/ w ch ar ac t er b or d er / s ha d ow s el ec t i o n. 1: s h ad ow 0: bo r d er 0 3 r / w o s d w i ndo w #n cha r ac t e r bo r d e r/shado w co lo r look - u p tab l e se l e cti o n 0 0x 0 a d 2 - 0 r / w o s d w i ndo w #n char ac t e r bor d e r/shado w co lo r cont r o l 000 add r ess bit r/w des c ription reset 7 - 4 r/ w res er ved. 0000 3 r/ w ch ar acter v-space inside window #n (1 scan line per step) msb bit. 0 2 r/ w ch ar acter h-space inside window #n (1 pixel per step) msb bit. 0 1 r/ w os d window #n shadow width msb bit. 0 0x 0 a e 0 r/ w os d w i n d ow # n bor d er c ol or w i dt h ( 1 pi x el or s c a n l i n e p er s t e p ) m sb bi t . 0
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 74 r ev. a 0 2 /05 /20 08 0x0b0 to 0x0c6 ? panel control address bit r/w description reset 7 r/ w res er v e d 0 6 r/ w set pi n f pde a c t i v e h i g h 0 : act i v e l o w 1 5 r/ w set pi n f phs a c t i v e h i g h 0 : act i v e l o w 0 4 r/ w s e t p i n fp vs a c ti v e h i g h 0 : a c tiv e l o w 0 3 r/ w i n v e rt p i n f p c l k p o l a rit y 0 : o u t put si g nal s t o f l at p a n el ( fp vs, fphs, ? et c . ) ar e r ef e r e n c e d t o t h e f a l l i ng e dg e of fpclk. 0 2 r/ w re s erv ed 0 1 r/ w r e v e r se t h e b i t or de r on pane l dat a bus. 0: m s b is on f pr[7 ], f p g[7 ], f pb[ 7]. 1 : m s b is on f pr[0 ], f p g[0 ], f pb[ 0]. 0 0x 0 b 0 0 r/w s w app i n g r ed an d bl ue d ata bus 0 : no sw appi n g 1 : dat a bus sw appi n g r e d a nd bl u e 0 addr e s s bit r/w des c ription reset 7 r/ w tcon m od e s el ect 1 : al l of th e p anel out p u t pi ns as si gn to tco n i n t e r f ac e s i g n al s. ** ref er timing controller shared pin description after pin description 00 6 r/ w set t hi s bi t t o 1 m a ki n g fp c lk b e c o m e i n act i v e dur i n g v er t i cal bl a nki ng t i me. 0 5 r/ w de mod e s el e c t i o n. 1: f pv s a n d f phs ar e f or c e d t o i nac t i v e st at e. 0 4 r/ w f p da t a ou t p u t s shi ft dow n 2 bi ts. w h e n set, f p r0 , fpr1 , f p g0, fp g 1 , fp b 0 , fp b1 bus si gna ls ar e s hi f t e d d ow n b y 2 bi t s . 0 3 r/ w tri-st ate a l l the o u t p u t si g nal s t o fl at pa nel . 0 0x0b 1 2 - 0 r/ w p ane l cloc k f pclk de l a y tim e se l e c t ion . 00 0: n o del ay t i me i ns er t e d. e ac h i n c r e m e n t i n c r e as e s t h e del ay by 1 n s . 0 00 address bi t r/w des c r i ption reset 0x 0 b 2 7 - 0 r/ w fp hs p er i od - low byte 0011 1010 add r ess bi t r/w des c r i ption reset 0x 0 b 3 7 - 0 r/ w f p h s activ e p u lse w i dt h th is r e g i ste r is u s ua ll y f i ll e d in w i th the m i n i m u m f p h s pu ls e w i d t h r e quir e m ent fr om t h e fl a t pane l s p eci f i c at ion 0001 0000 addre s s bi t r/w des c r i ption reset 0x 0 b 4 7 - 0 r/ w fl at p an el hor i z on t al b a ck p or c h w i dt h - - - t h e d ur at i o n f r om t h e t r ai l i ng e d ge of fp hs t o t he lead ing ed ge o f fp d e . t hi s r e gi s ter is usually filled in with the minimum horizontal back porch requirement from the flat panel specification. 0001 1011 addre s s bi t r/w des c r i ption reset 0x 0 b 5 7 - 0 r/ w fp de hor i z o ntal active length 0000 0000
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 75 r ev. a 0 2 /05 /20 08 address bit r/w description reset 7 r/ w w h en t h i s b i t is set, the i n t e r n a l circ uitry u se s the p r og r a m m e d v a l u e o f i n d e x b 6 [ 3 : 0 ] and inde x b2[ 7 : 0] as t he f p hs p er i o d di sr e g ar di n g t he s et t i n g of ? a ut o c al c u l at i o n? , bi t 1 of i nd ex b e . 0 6 - 4 r/ w fp de hor i z o nt al a c t i v e l e ngt h ? hi g h t hr e e bi t s ( t ot a l 1 1 bi t s ) t hi s hor i z o nt al ac t i v e l e n gt h i s e q ui v al e nt t o t he p a nel h or i z ont al r es ol u t i o n. f or ex a m pl e, t h e h o r iz o n t a l r e so l u ti on o f an xg a pa ne l is 1 024 . 100 0x 0 b 6 3 - 0 r/ w fp hs p er i od ? hi g h t hr e e bi t s ( t ot al 1 2 bi t s ) t he f ol l ow i ng f or m ul a gi v es t h e c or r e c t n u m be r t o f i l l i n f or fp hs p er i o d. fp hs _ p er i o d = f _pl l c ki / ( f _ i hs y n c * vs ur ) wh e r e f _ p l l c ki i s t h e fr eq uenc y o f e x t c l k , f _ i h s y n c is the fr eq uenc y o f i n pu t h s y n c , and vs ur i s t h e v er t i cal s c al e u p r a t i o. v s u r = (pane l ve rti ca l re so l u tion ) / ( i n p u t ve r t ica l reso lu ti o n ) e x am p l e : i npu t is vg a wi th h s y n c frequen cy 3 1 . 5kh z w i th 60 hz r e fr es h r a te t o be d i spl a y e d o n a n x g a pane l. vs ur = 76 8/ 4 8 0 = 1 . 6 c hoose f _p ll cki = 69 m h z f p h s _ p e r i od = 6 9000 000 / (315 00 * 1 . 6 ) = 13 69 . 05 1 369 = 559h 0010 no t e : th e un i t fo r i n de x b2 t h r o ugh b 6 i s one pane l p i x e l clo ck , w h ic h i s e i t h e r t h e ou t p u t of i n t e r n a l pll o r ex t c l k . the fphs period should be larger than the sum of 1) fphs active pulse width, 2) fphs back porch width, and 3) fpde horizontal active length. address bit r/w description reset 0x0b7 7 - 0 r/w fpvs period - low byte 0010 0110 address bit r/w description reset 0x 0 b 8 7 - 0 r / w f p vs ac ti v e pu l s e w i dt h t he u ni t of t hi s p ul s e w i dt h i s o n e f p hs . th is r e g i ste r is u s ua ll y f i ll e d in w i th the m i n i m u m f pvs p u l se w i d t h r equirem ent fr o m t h e fl a t pan e l s p eci f i c at i o n. 0000 0110 address bit r/w description reset 0x 0 b 9 7 - 0 r/ w fl at p an el v er t i c al ba c k p or c h w i dt h t he u ni t of t hi s p ul s e w i dt h i s o n e f p hs . t he f ol l ow i ng f or m ul a gi v es t h e c or r e c t n u m be r t o f i l l i n f or fpv s b ac k p or c h . f p vs_ba c k _ p o r c h = (va s ? vsy n c _p w + 2 )* vs ur? fpv s _ p u l se_w i dt h w h er e v a s i s t he i npu t ve rti ca l a ctiv e st a rti n g l i n e nu mbe r, vsy n c _p w is t h e i n put v s y n c pu lse w i dt h, vs ur i s t h e v er t i c al s c al e u p r at i o. v s u r = (pane l ve rti ca l re so l u tion ) / ( i n p u t ve r t ica l reso lu ti o n ) 0001 1111 address bit r/w description reset 0x0ba 7 - 0 r/w flat panel vertical active length - low byte 0000 0000 address bit r/w description reset 7 r/w early start. start to output data earlier in non auto calculation mode. 0 6 - 4 r / w f l a t p a ne l ve rti ca l a ctiv e leng t h - h i gh t h r e e b i ts (t o t al 1 1 b i ts ) th e un i t o f t h i s ac t i v e l e ng t h i s on e fph s th is v e rti c a l a c tiv e leng th i s equ iv a l en t t o t h e pa ne l v e rti c a l r e so l u ti on. for e x a m p l e , t h e v e rti c a l r es ol ut i o n of a n x g a p a nel i s 7 68. 011 3 r/w this bit is for internal used. 0 0x 0 b b 2 - 0 r/ w fpv s p er i o d ? hi g h t hr e e bi t s ( t ot a l 1 1 bi t s ) t he u ni t of t hi s p er i od i s o n e fp hs . 011 note: the unit for index b7 through bb is one fphs, i.e. whenever there is an active fphs, the count is incremented by 1. the f pvs period should be larger than the sum of 1) fpvs active pulse width, 2) fpvs back porch width, and 3) flat panel vertical active length . note: the value written in this register does not come into effect until it is followed by a register write to index 0x0b7 or 0 x0ba.
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 76 r ev. a 0 2 /05 /20 08 address bit r/w description reset 7 r / w th is is p i x e l do ub l e f unc ti on fo r v e rti ca l sca l i ng. en a bl e t hi s bi t , t h e h o r i z ont al s c al i n g r at i o r e gi s t er v al u e m u s t s e t ex act l y tw o t i mes. 0 : d i sab l e , 1 : e n ab l e 0 6 - 4 r / w d i t h e r op ti o n cod e "010 " is r e c o m m ended f o r 6 : 6: 6 ou tpu t 00 0 3 r / w th is is li ne d oub l e func ti o n f o r v e r t ical sca l i ng . en a bl e t hi s bi t , t h e v er t i cal sc al i n g r at i o r e gi s t er v al u e mu s t s et ex a c t l y tw o t i mes . 0 : d i sab l e , 1 : e n ab l e 0 0x 0 b c 2 - 0 r / w d i t h e r ou t p u t fo r m at se l e c t i o n "001 " is r e co m m ended f o r 6 : 6: 6 ou tpu t 000 ta b l e 6 d i the r o u tput se le c t ion an d c a lcu lat ion s di t h er ou t p ut fo r m at s e le c t io n fl at p an el rg b bi t fo r m at ou t p ut di t h er op t i o n c ode i n put l s b s u sed in di t her c a l c ul at i o n di t h er me t h o d di t h er ou t put fo r m at s e le c t io n fl at p an el rg b bi t fo r m at ou t p u t di t h er op t i on c o de i n put l s b s u sed in di t her c al c ul at i o n di t h er me t h o d 000 8:8:8 x xx n / a none 00 1 ( 4) ( 4) ( 4) 2x 2 001 ( 1 ) (1 ) ( 1 ) 2 x 2 0 1 0 (4 , 3 ) (4 ,3 ) ( 4 ,3 ) 2 x 2 001 6: 6: 6 0 1 0 (1 , 0 ) (1 ,0 ) 2 x 2 0 1 1 (4 ,3 ,2 ) (4 ,3 ,2 ) (4 ,3 , 2 ) 2 x 2 001 ( 2 ) (1 ) ( 2 ) 2 x 2 1 01 3: 3: 3 1 0 0 ( 4 ,3 ,2 ,1 ) (4 ,3 ,2 , 1 ) (4 ,3 , 2 ,1 ) 4 x 4 01 0 (2 ,1 ) (1 ,0 ) ( 2 ,1 ) 2 x 2 00 1 ( 4) ( 4) ( 5) 2x 2 010 5: 6: 5 0 1 1 ( 2 ,1 ,0 ) (1 ,0 ) (2 ,1 ,0 ) 2 x 2 0 1 0 (4 , 3 ) (4 ,3 ) ( 5 ,4 ) 2 x 2 001 ( 2 ) (2 ) ( 2 ) 2 x 2 0 1 1 (4 ,3 ,2 ) (4 ,3 ,2 ) (5 ,4 , 3 ) 2 x 2 010 (2 ,1 ) (2 ,1 ) ( 2 ,1 ) 2 x 2 1 10 3: 3: 2 1 0 0 ( 4 ,3 ,2 ,1 ) (4 ,3 ,2 , 1 ) (5 ,4 , 3 ,2 ) 4 x 4 011 5:5: 5 0 1 1 ( 2 ,1 ,0 ) (2 ,1 ,0 ) (2 ,1 , 0 ) 2 x 2 001 (3) (3 ) ( 3 ) 2 x 2 010 (3 ,2 ) (3 ,2 ) ( 3 ,2 ) 2 x 2 011 ( 3 ,2 ,1 ) (3 ,2 ,1 ) (3 ,2 , 1 ) 2 x 2 100 4: 4: 4 100 ( 3 ,2 ,1 , 0 ) (3 ,2 , 1 ,0 ) ( 3 ,2 ,1 , 0 ) 4 x 4 addres s bit r/w description reset 0x 0 b d 7 - 0 r/w output vsync delay from input vsync 0000 1000 add r e ss bit r/w description reset 7 r/ w force long. in auto calculation with this bit set, the fphs period assumes the next higher integer value if the calculated fphs contains fractional part. 0 6 r / w fo rce sho rt. in auto ca lc u l ati o n w i th i s b i t set, t h e f phs pe ri od a s sum e s the i n tege r pa rt; i . e . the fra cti o n a l pa r t o f the ca l cu l a t e d fphs pe ri od i s d i s ca r ded . 0 5 r/ w tri-state pwm pin. 0 4 r /w pwm polarity. 1: active low 0 3 r /w when set, the input ?hactive? or ?de? is forced to inactive if either vsync or hsync is active. 0 2 r /w force into free run mode. 0 1 r/ w enable auto calculation. when this bit is set, an internal circuitry calculates the optimum fphs period, and then adjusts the fphs period dynamically so that for one vsync (fpvs) period it has integer multiples of fphs. the internal circuitry also adjust the fphs active position to minimize the line buffer overflow/underflow. 0 0x 0 b e 0 r / w w h en t h i s b i t is set, the i n p u t vs y n c i s de l a y e d b y th e am ount spec i f ied b y in de x 0 x bd in t h e un it o f i npu t h s y n c . the r e gu l a r m eani ng o f i nde x 0 x b d - - ?ou t pu t vs y n c de l a y fr o m i n p u t v s y n c ? i s f i x ed at 2. 0
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 77 r ev. a 0 2 /05 /20 08 address bit r/w description reset 7 - 6 r/w di s p l ay si ngl e f i el d o n f l at p a nel . 0x : f u nct i o n di s a bl e d. 10 : di s pl ay od d f i el d. 11 : di s pl ay ev en f i el d. 00 5 r/w w h e n s et t h e f i el d si g nal i s r ev er s e d i n t h e a ut o c al c ul at i on c i r c ui t r y . 0 4 r/w sel e c t di f f er e nt v e r t i cal sy n c s o ur c e i n si ngl e f i el d i n p ut . 0 3 r/w no ev e n f i el d i ni t i a l i z at i o n 0 0x 0 b f 2 - 0 r/w even field delay. 001= +1, 010= +2, ? 101= +5, 110= -1, 111= -2 000 address bit r/w description reset 0x0c0 7 r/w bits 8 to 1 of 13 bit counter ? c2(3-0), c0(7-0) 0000 0000 address bit r/w description reset 0x0c1 7 r/w bits 8 to 1 of 13 bit counter ? c2(7-4), c1(7-0) 0000 0000 address bit r/w description reset 7 - 4 r/ w u ppe r 4 b i ts ( b i t s 13 t o 9 ) o f 13 b i t c o un t e r ? c2 ( 7 - 4 ), c1 ( 7 - 0 ) fo r non - f r e e - run m o d e , t h i s spec i f i e s t h e uppe r 12 - b its o f t h e i n i t i a l v a l u e o f a 1 3 -b i t co u n te r fo r th e e v e n f i e l d . for free-run with calibrate bit set, this specifies the value for the vertical line counter to load at the falling edge of input vsync. 0000 0x 0 c 2 3 - 0 r/ w u ppe r 4 b i ts ( b i t s 13 t o 9 ) o f 13 b i t c o un t e r ? c2 ( 3 - 0 ), c0 ( 7 - 0 ) fo r non - f r e e - run m o d e , t h i s spec i f i e s t h e uppe r 12 - b its o f t h e i n i t i a l v a l u e o f a 1 3- bi t c ou nt er f or t h e od d f i el d. for free-run with calibrate bit set, this specifies the value for pixel counter to load at the falling edge of input vsync. 0000 address bit r/w description reset 7 - 6 r/ w ev en f i el d v er t i c al st ar t p oi nt a dj u s t me nt . 00 : e v en f i el d st ar t w i t h t h e s a me l i ne c o u nt s p e c i f i e d i n 0x as o dd f i el d. 01 : e v en f i el d st ar t w i t h o n e ex t r a l i n e c o u n t s p ec i f i e d i n 0x c 1. 10 : e v en f i el d st ar t w i t h o n e l es s l i n e c o unt s p ec i f i e d i n 0x c1 . 00 0x 0 c 3 5 - 0 r/ w res er v e d 00 0 0 00 address bit r/w description reset 7 r / w p w m c l o ck se l e ction 0 : 27 m h z (x t a l27 i i npu t fr e quency) / 1 2 8 1: ( 2 7/ 2m hz ) / 1 2 8 0 0x 0 c 4 6 - 0 r/ w po si t i v e pul s e w i dt h of t h e p w m . i f t hi s r e gi s t er h as an ? n ? v al u e, t h e po s i t i v e p ul s e w i dt h d ur at i on i s ? n + 1? p w m c l oc k s . 100 0 000 address bit r/w description reset 0x 0 c 5 7 - 0 r/ w res er v e d. 00h address bit r/w description reset 0x 0 c 6 7 - 0 r/ w res er v e d. 00h address bit r/w description reset 7 r/ w p w m 2 cl oc k s el e c t i o n 0 : 27 m h z (x t a l27 i i npu t fr e quency) / 1 2 8 1: ( 2 7/ 2m hz ) / 1 2 8 0 0x 0 c 7 6 - 0 r/ w po si t i v e pul s e w i dt h of t h e p w m 2. if th i s reg i ste r ha s a n ? n ? v a lue , t h e p o sitiv e pu l s e w i d t h du r a ti o n i s ? n +1 ? p w m 2 cl o cks. 100 0 000
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 78 r ev. a 0 2 /05 /20 08 low s peed adc a nd mcu con tro l reg ist ers 0x 0c8 to 0x0ca ? l adc and mcu c ontrol r eg i sters address bit r/w description reset 7 r/w reserved. 0 6 - 5 r/w mcu debug mode control bit 0 4 r/w ladc_pd_cmp control bit 0 3 r / w l adc_ p d cont r o l bi t 0 0x 0c 8 2 - 0 r/ w hi g h er 3 bi t s of la d c cl oc k di v i de v al u e. di v v al ue = { 0x 0 c 8[ 2: 0] , 1 0 01} . d e f a u l t l a d c clock fr equ en cy = 27 / 9 = 3 m h z 0 00 addr e s s bit r/w description reset 0x 0c9 7 - 0 r/w ladc channel 0 input value 0 add ress bit r/w description reset 0x 0ca 7 - 0 r/w ladc channel 1 input value 0 0x 0d0 to 0x0d3 ? sta t us and interrupt re g isters add r e s s bit r/w name description reset 7 r line buffer over flow th is b i t is se t if t h e f p c l o ck cou n t e x c e ed s t h e m a xi m u m n u m b e r i n betw een t w o co ns ecut i v e fp h s p u l ses f o r t h e ev en fi e l d , cl e a r e d b y w r i t i ng back a "1 ". - 6 r l i ne b u ff er under flow t his bit is set if the fp clock count exceeds the maximum number in between two consecutive fphs pulses for the odd field, cleared by writing back a "1". - 5 r in put vsy nc loss st at u s c h an ge d thi s b i t i s s e t w hen th e st at u s bi t of "i np u t vsy nc l o s s " h ad c hang ed, ei t her 1 t o 0 or 0 t o 1. t h i s b i t i s c l e ar ed by w r i t i ng b ack a "1", or by re se tting th e " e n d e t " b i t . - 4 r in put h s y nc loss st at u s c h an ge d thi s b i t i s s e t w hen th e st at u s bi t of "i np u t h s y n c loss " ha d c h a n ge d , ei t her 1 t o 0 or 0 t o 1. t hi s bi t i s cl ear e d by w r i t i n g back a " 1 ", o r by r eset t i ng t h e " e n det " bi t . - 3 r/ w vi deo i n put st a t us c ha ng ed in d i ca tion vdl o s s status bit change (register 1 bit 7) or det50 status bit change (register 1 bit 0) write a one to this bit to reset. 0 2 r in put vsy nc loss thi s b i t i s s e t w hen th e i n p u t vsy nc p u l s e i s l o st , r e s e t by r e - ap pear anc e of v s y n c. an 1 1 - bi t cou nt er i s us ed f or vsy nc p e r i od m e as ur e m e n t . i f t h i s c ount er o v erf l o w s 4 ti m e s, t h e vs y nc i s co n s i der ed t o be l o st . - 1 r in pu t hsy n c lo s s th i s b i t i s set w h en t h e i n p u t h s y n c pu l se i s l o st, r e se t b y re - a ppea r a n c e o f h s y n c . a n 1 1 - b i t coun t e r is u sed for h s y n c pe ri od m e as u r em ent. if t h i s coun t e r o v e rfl o w s 4 ti m e s, t h e h sync i s con s i d e r e d t o be l o st. - 0x0 d 0 0 r s y nc d e t ect st at us log i c func ti on o f: in v e r t ed ? b i t 1 ? and i n g w i th i n v e rted ? b i t 2 ? - a d dress bit r/w name desc r iption reset 7 r in put m e asur emen t dat a re ady thi s bit is set when the measurement data is ready for readout, reset when a new "startm" is set. - 6 r pow e r st at e chan ge d thi s b i t i s s e t w hen th e p o w e r m a na gemen t st at e h a s c h a n g ed, r e s e t by w r i t i ng back a "1 ". - 0x0d 1 5 r in put vsy nc per i od ch an ge det ect ed thi s b i t i s s e t w hen th e i np u t vsy nc p er i od i s c h an ged, r es e t w he n " e n det " i s c l ear e d . w h e n " e n det " bi t i s set, t h e v s y n c p e r i o d i s m e as ur e d f o r ev e r y fr a m e. i f t he d i ff er en c e f r o m t h e l a s t m e as ur emen t re su l t s to r e d i n the reg i s te rs , is la rge r th an t h e e rro r to l e ran c e , the vsy n c per i o d i s co nsi de r e d t o h av e c h a ng ed. - del e t e d : fp h s ma x cl oc k v i ol at i on i n e v en f i el d del e t e d : fp h s ma x cl oc k v i ol at i on i n od d f i el d del e t e d : re se rv e d
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 79 r ev. a 0 2 /05 /20 08 address bit r/w name description reset 4 r in put h s y nc per i od ch an ge det ect ed thi s b i t i s s e t w hen th e i n p u t h s y n c per i o d i s c h an ged, r e s e t w hen " e n det " i s c l ear e d . w he n " en det " bi t i s set, t h e hs y n c pe r i od i s m e as ur e d f o r ev e r y sc a n l i n e . if t he di f f er enc e f r om t h e l ast m e as ur e m e n t r e sul t st o r e d i n t he r egi st er s, i s l a r g e r t han t h e er r o r t o l e r anc e, th e h s y n c p e r i od i s c onsi der ed to hav e c h an ged. - 3 r line buffer overflow or underflow - 2 r vdccdet high if there is a change in vdloss or det50 or ccvalid - 1 r vloss/ hloss st at us c h an ge d thi s b i t r ef l ect s t h e ? o r? c on d i t i o n o f st a t u s bi t i ndex b0 bi t 5 ( v lo ss st at us cha ng ed) an d i nd e x b0 b i t 4 ( h loss st a t u s c ha ng e d) . - 0 r " s y n c det ect st a t us " chan ge d thi s b i t i s s e t w hen th e st at u s bi t of "sy nc d e t e ct s t at u s " ha d c h an ged, ei t her 1 t o 0 or 0 t o 1. t h i s b i t i s c l e ar ed by w r i t i ng b ack a "1", or by re se tting th e " e n d e t " b i t . - a ddress bit r/w description reset 7 r/ w ena bl e/ di s a bl e 0 x 0d1 bi t 7 as a n i rq s o ur c e 0 : e nabl e 1 : di sa b l e 1 6 r/ w ena bl e/ di s a bl e 0 x 0d1 bi t 6 as a n i rq s o ur c e 0 : e nabl e 1 : di sa b l e 1 5 r/ w ena bl e/ di s a bl e 0 x d 1 bi t 5 as an i r q s o u r c e 0 : e nabl e 1 : di sa b l e 1 4 r/ w ena bl e/ di s a bl e 0 x d 1 bi t 4 as an i r q s o u r c e 0 : e nabl e 1 : di sa b l e 1 3 r/ w ena bl e/ di s a bl e 0 x d 1 bi t 3 as an i r q s o u r c e 0 : e nabl e 1 : di sa b l e 1 2 r/ w ena bl e/ di s a bl e 0 x d 1 bi t 2 as an i r q s o u r c e 0 : e nabl e 1 : di sa b l e 1 1 r/ w ena bl e/ di s a bl e 0 x d 1 bi t 1 as an i r q s o u r c e 0 : e nabl e 1 : di sa b l e 1 0x0d 2 0 r/ w ena bl e/ di s a bl e 0 x d 1 bi t 0 as an i r q s o u r c e 0 : e nabl e 1 : di sa b l e 1 a ddress bit r/w description reset 7-3 r/w reserved. - 2 r/ w ena bl e/ di s a bl e v d loss a s a n i rq so u r c e 0 : e nabl e 1 : di sa b l e 1 1 r/ w ena bl e/ di s a bl e ccv ali d as an i rq s our c e 0 : e nabl e 1 : di sa b l e 1 0x0d 3 0 r/ w ena bl e/ di s a bl e det 50 a s a n i rq so u r c e 0 : e nabl e 1 : di sa b l e 1 deleted: interrupt request status
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 80 r ev. a 0 2 /05 /20 08 0x0d4 to 0x0d8 ? power management registers address bit r/w description reset 0x 0 d 4 7- 0 r / w m s b of a n i nt er n al 2 3 bi t di v i de d ow n c ou nt er . t h e 27 m h z cl oc k f r o m x ta l 2 7i i s di v i de d by t hi s coun t e r to s e rv e as t h e c l o ck f o r the po w e r sta t e tr a n siti on ti m e r. 0000 0000 address bit r/w description reset 7 r / w f o r c e th e in te rn a l p c l k to ?0 ? . 0 6 r / w p o w e r sequ en c e r e fe r ence s o u r ce se l e cti o n . 0 : 27 m h z 1 : vsync 0 5 - 4 r sh ow c ur r e n t p ow er ma n ag e m e n t st at e. t h es e p ow er st at es d e t er m i n e t he s t at es o f pi n s f p p w c, fp bia s & fp i n t e r f ace si gna ls w h i c h i n c l u des fpv s , f p h s , fp d e , fpcl k and a l l dat a s i g n al s . f ppw c f p b i as f p i n te r f ac e s i gna ls 00 : o ff ?0 ? ?0 ? ?0 ? 01 : s tandb y ?1 ? ?0 ? ?0 ? 10 : s u sp e n d ?1? ?0 ? ?1 ? o r ?0 ? 11 : on ?1 ? ?1 ? ?1 ? o r ?0 ? the tr ans i t i o n be tw ee n t h e p o w e r st at es do es n o t oc c u r r i ght a w ay . it t a k e s p l ac e a f t e r t h e ti m er ex pi r atio n by t h e c or r esp on di ng t i m er c o u n t s d e f i n ed i n 0x d6 - 0 x d 8. 00 3 r/ w m a n u a l po w e r seq uenc i n g c o n t r o l . w hen th i s b i t is set, b i ts [ 2 : 0 ] c o n t r o l f p b i as , f p i n t e r f a c e s i gn a l s , and f ppw c d i r e ctly . 0 2 r / w if b i t 3 i s ? 0 ? and t h is b i t i s ? 1 ? , t h i s enab l e au to po w e r s eque ncing . vs y nc l o s s & hs y nc l os s - - - > of f vs y nc l o s s & hs y nc a c t i v e - - - > s t an d by vs y nc act i v e & hs y nc l os s - - - > s us p en d v s y n c a c ti v e & h s y n c a c tiv e ---> on 0 0x 0 d 5 1 - 0 r / w pow er st at e s t e er i ng. w he n t h es e 2 bi t s ar e w r i t t en, a s s u m i ng b ot h bi t 3 a nd bi t 2 ar e 0? s, a nd t h e c ur r ent p ow er st at e i s di f f er e nt f r o m t h e v al ue w r i t t en, t he p ow er st at e w i l l b e s e q ue nc i n g t o t h e st at e t hat ma t c h es t h e v al u e w r i t t en. f or ex a m pl e, c ur r e nt p ow er st at e i s 1 1. a 0 1 v al u e i s w r i t t en. t he p ow er st a t e w i l l be s t e er e d t o ? 0 1? an d s t ay i n ? 0 1. 0 0 : off s t at e , 01 : s t andb y , 10 : su spen d , 11 : on s t a t e 00 addres s bit r/w des c r i pt ion reset 7 - 4 r / w t i m e r counts for suspend state to standby state transition 0000 0x 0 d 6 3- 0 r / w t i m e r cou n t s f o r o n s t a t e t o s u spen d s t a t e tr a n siti on 0000 add r e s s bit r/w des c r i pt ion reset 7 - 4 r / w t i m e r counts for power off state to standby state transition 0000 0x 0 d 7 3- 0 r / w t i m e r cou n t s f o r s t andb y s t at e t o po w e r o ff s t a t e tran s i ti on 0000 add r e ss bit r/w des c r i pt ion reset 7 - 4 r / w t i m e r counts for standby state to suspend sate transition 0000 0x 0 d 8 3- 0 r / w t i m e r cou n t s f o r s u spend to on st a t e t r a n siti o n 0000
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 81 r ev. a 0 2 /05 /20 08 0x 0da to 0x0df ? c o lo r enhanc eme nt address bit r/w description reset 0x 0 d a 7 - 0 r / w c o l o r enhan cem e n t ce n t e r co l o r p hase f o r c o l o r 1 . the r a n g e f o r cen t e r co l o r pha s e is ?180 ~ + 1 80 , 2 deg r ee per s t ep . 3dh addr e s s bit r/w description reset 0x db 7 - 0 r / w c o l o r enhan cem e n t ce n t e r co l o r p hase f o r c o l o r 2 . the r a n g e f o r cen t e r co l o r pha s e is ?180 ~ + 1 80, 2 degree per step. c3h add ress bit r/w description reset 0x dc 7 - 0 r / w c o l o r enhan cem e n t ce n t e r co l o r p hase f o r c o l o r 3 . the r a n g e f o r cen t e r co l o r pha s e is ?180 ~ + 1 80, 2 degree per step. fch add ress bit r/w description reset 7 r/w 1: color enhancement enable, 0: disable 0 6- 5 r/ w c o l o r enhan cem e n t gain s p r e ad rang e f o r col o r 1 0 0 : no e nhan ce 01 : - 8 ~ +8 of c e nt er c ol or ph as e 10 : - 16 ~ +16 of c e n t e r co l o r phase 11 : - 32 ~ + 3 2 o f c ent er c ol or p h as e 00 0x0 dd 4 - 0 r / w c o l o r enhan cem e n t ga in f o r c o l o r 1. the m i n i m u m ga i n v a lue is 0 0000 and m a x i m u m i s 11 111 f r o m 0 t o 0. 48 4 w i th 3 1 st e p of 1 / 6 4 . 0000 add r e ss bit r/w description reset 7 r/ w res er v ed 0 6- 5 r/ w c o l o r enhan cem e n t gain s p r e ad rang e f o r col o r 2 0 0 : no e nhan ce 01 : - 8 ~ +8 of ce nt er c ol or ph as e 10 : - 16 ~ +16 of c e n t e r co l o r phase 11 : - 32 ~ + 3 2 o f c ent er c ol or p h as e 00 0x0de 4- 0 r / w c o l o r enhan cem e n t ga in f o r c o l o r 2 . the m i n i m u m ga i n v a lue is 00 000 a n d m a x i m u m i s 111 11 f r o m 0 t o 0. 48 4 w i th 3 1 st e p of 1 / 6 4 . 0000 address bit r/w description reset 7 r/w reserved 0 6- 5 r/ w c o l o r enhan cem e n t gain s p r e ad rang e f o r col o r 3 0 0 : no e nhan ce 01 : - 8 ~ +8 of c enter c ol or ph as e 10 : - 16 ~ +16 of c e n t e r co l o r phase 11 : - 32 ~ + 3 2 o f c ent er c ol or p h as e 00 0x0df 4-0 r/ w c o l o r enhan cem e n t ga in f o r c o l o r 3. the m i n i m u m ga i n v a lue is 0 0000 and m a x i m u m i s 11 111 f r o m 0 t o 0. 48 4 w i th 3 1 st e p of 1 / 6 4 . 0000 0x0e0 ? etc addr bit r/w de s c r i pt i on reset 7 r / w li n e buf f er ov erflow/underflow status report method. 0 6 r / w pi x el cl oc k c ou nter selection for field selection for field detection circuitry. 0 5 r/w reserved. 0 4 r / w d i s a b l e se ri a l bu s inde x add r e ss i n c r e m ent du ri ng mu lti p l e da t a w r i t e /read . 0 3 - 1 r / w r e s e rv ed. 000 0x0e0 0 r/w enable f o r w r it e sequ ence r e g i s t e r m o de 0
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 82 r ev. a 0 2 /05 /20 08 0x0f0 ? gamma address bit r/w description reset 7 r/w enable red gamma correction. 0 6 r/w enable green gamma correction. 0 5 r/w enable blue gamma correction. 0 4 r/w reserved. 0 3- 2 r/ w e nab l e ga m m a t a b l e add r e ss a u t o i n crem ent f o r r ead ing / w r i t in g gam m a d a t a po rt. 0 0 : d i sab l e , 01 : r ead on ly , 1 0 : w r i t e on l y , 11 : re ad / w r i t e 00 0x 0 f 0 1 - 0 r / w g a mm a tab l e s acce ss se l e c t i o n : i nd ex a d d r e ss 0x 0 f 1 t o 0x 0f 2 ar e u s e d f or g a mma t a bl e ac c es s es . t h er e ar e 3 s et s of g a mma ta b l e , one tab l e f o r one c o l o r, sha r i n g t h e sam e ad d r e ss po rt a n d da t a po rt. t h ese 2 b i ts i d e n t i f ie s w hi c h t a bl e i s a c c es s e d. 0 0 : rg b gamm a tab l e 01 : re d g a mm a t a b l e 1 0 : gr e e n gamm a t a b l e 11 : b l ue gamm a t a b l e 00 address bit r/w description reset 0x 0 f 1 7 - 0 r / w g a mm a tab l e addre ss p o r t. 0000 0000 address bit r/w description reset 0x 0 f 2 7 - 0 r / w ga m m a t a bl e d at a por t . - address bit r/w description reset 0x 0 f 3 7- 1 r/ w r e s e r v e d - 0 r/w adc y channel gain adjust high register 0 address bit r/w description reset 0x 0 f 4 7 - 0 r / w a d c y c han ne l ga i n ad j u s t lo w r eg i st e r 00
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 83 r ev. a 0 2 /05 /20 08 0x0f5 ? dac control address bit r/w description reset 7:5 r/w * 0x 0 f 5 4-0 r/w dac r channel gain 00 00 00 00 0x0f6 ? dac control address bit r/w description reset 7:5 r/w * 0x 0 f 6 4-0 r/w dac g channel gain 00 00 00 00 0x0f7 ? dac control address bit r/w description reset 7:5 r/w reserved 0x 0 f 7 4-0 r/w dac b channel gain 00 00 00 00 0x0f8 ? dac control address bit r/w description reset 7 r/w dac power down 6-1 r/w * 0x 0 f 8 0 r/w daciref 00 00 00 00
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 84 r ev. a 0 2 /05 /20 08 0x0f9 to 0x0fe ? spread spectum synthesizer control registers address bit r/w description reset 7- 6 r / w i nt er nal op er at i ng c l o c k s el e ct i o n 2 ? h0 : s s -pll ou tpu t cl o ck 2 ? h1 : 2 7 m h z xtal 2 ? h2 : e x t _ c k 2?h3 : reserved 0x0f 9 3 - 0 r / w f p ll [ 1 9 : 16] p ll o scil l a t i on freq uenc y = 108 m h z * f p ll / 2 ^ 17 0 0h address bit r/w description reset 0x0fa 7-0 r/w fpll[15:8] 40h address bit r/w description reset 0x0fb 7-0 r/w fpll[7:0] 00h address bit r/w description reset 0x 0 f c 7- 0 r/ w fss [ 7- 0] , s p r ead spe ctrum m odu l a ti on fr equ enc y = 27 m h z * f s s / 2 ^ 1 6 4 0h address bit r/w description reset 7 r/ w pd _ ss p l l, p l l pow er d ow n c o nt r ol . 1 = p o w er dow n 6- 4 r/ w ss d, s pr e ad s p e c t r u m g ai n di v i der . 0x 0 f d 3- 0 r/ w ss g, s pr e a d s p e c t r u m gai n c o nt r ol . fr e qu e nc y dev i at i o n c o nt r ol : th e m a x p e r cen t ag e o f freque ncy de v i a t i o n is g i v e n by fo ll o w in g eq ua ti o n . dev = 2^ 8 * ss g / 2^ s sd / 2^ f pl l * 1 0 0 % 3 0h address bit r/w description reset 7- 6 r/ w p l l pos t di v i der 0 ? 1 1 ? ? 2 ? ? 3 ? 1/8 5- 4 r/ w vc o r a ng e 0 0 : 13 . 5 ~ 27 m h z , 01 : 27 ~ 54 m h z 1 0 : 54 ~ 108 m h z , 11 : 10 8 ~ 2 1 6 m h z 3 r/ w 0x 0 f e 2- 0 r/ w ch ar g e p ump c ur r ent s ( ua) 3? b 0 00 : 1 . 5 3? b 0 01 : 2 . 5 3 ? b01 0 : 5 3 ? b01 1 : 10 3 ? b10 0 : 20 3 ? b10 1 : 40 3 ? b11 0 : 80 3?b111 : 160 1 1h 0x 0ff (or 0 x1ff) address bit r/w description reset 7-1 r/w reserved 00 0x 0 f f / 0x 1 f f 0 r / w index r egi s t er page s e lecti o n. 0: 0x 000~0x 0fe 1: 0x 100 ~ 0x 1fe 0
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 85 r ev. a 0 2 /05 /20 08 0x130 ? ccfl control i bit function r/w description reset 7 o v e n r/ w ov er v ol t ag e f e e db a c k c o nt r ol 0 = d i sab l e 1 = enab le 1 6 oien r / w o v e r c u r r e n t f eedb ack con t r o l 0 = d i sab l e 1 = enab le 1 5 u i e n r / w und e r cu rr en t f eed bac k con t r o l 0 = d i sab l e 1 = enab le 1 4 fb en r / w ccfl f e edba ck l oo p con t r o l 0 = open loop 1 = cl o s e l oo p 1 3 l o ckv r / w 0 = d i m m i ng fr eque ncy s e t b y f d im 1 = d i m m i ng fr eque ncy lo cked t o p ane l v e r t ica l sy n c. 0 2 l o ckh r / w 0 = p w m fr eq uenc y se t b y f p w m 1 = p w m fr eq uenc y l o c k ed to pan e l ho riz o n t a l fr equ enc y 0 1 c c f le nb r/ w 0 = c c f l p ow er u p 1 = c c f l p ow er d ow n. 1 0 c c f ld e n r/ w 0 = c c f l di s abl e. 1 = c c f l e na bl e . 0 0x131 ? ccfl threshold bit function r/w description reset 7-6 lvt r/w lamp voltage threshold 2h 5-4 lilt r/w lamp low current threshold 2h 3-0 lit r/w lamp normal current threshold dh 0x132 ? ccfl control ii bit function r/w description reset 7 le d_p d r/ w 0 = le dc p ow er up 1 = le dc p ow er dow n 0 6 le d_ di g _e n r/ w 0 = le dc di s a bl e 1 = le dc e n abl e 0 5-4 ccfl_ledc_st r/w ccfl or ledc status - 3-0 lstp r/w ccfl feedback gain control with 1 being the smallest gain. 4h 0x133 ? ccfl pwm bit function r/w description reset 7-0 fpwm r/w ccfl pwm control frequency 80h 0x134 ? ccfl dim frequency bit function r/w description reset 7-0 fdim r/w ccfl dimming frequency control. 84h
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 86 r ev. a 0 2 /05 /20 08 0x135 ? ccfl dim control bit function r/w description reset 7 fpbias_en r/w enable fpbias to pin#27 0 6 le dc _ o u t _s el r/w enable led_out to pin#10 0 5 ccfl_ out_ s el r/w enable ccflp to pin#10 and ccfln to pin#11 0 4-0 ddim r/w ccfl dimming control. 0=full brightness, 1f=lowest brightness 00h 0x136 ? pwmtop bit function r/w description reset 7-0 pwmtop r/w reserved 20h 0x137 ? spread spectum synthesizer control registers bit function r/w description reset 7-6 reserved r/w reserved 0 5-4 lp_x8 r/w loop resistor selection for pllx8 0 3-2 lp_x4 r/w loop resistor selection for pllx4 0 1-0 cp_x4 r/w charge-pump current selection for pllx4 0 0x140 to 0x141 ? gpo address bit r/w description reset 7 r/w enable pwm2 to pin#52 0 0 x 140 6- 0 r / w en a bl e f or gp 6 ? gp 0 0 address bit r/w description reset 7 r/w reserved 0 0 x 141 6- 0 r / w dat a f or gp 6 ? g p 0 0 0x 157 to 0x15a, 0x 1 f0 to 0x1 f 9 ? debu g r eg i sters address bit r/w description reset 0 x 157 0 x 158 0 x 159 0x 1 5 a 7 - 0 r t hes e f o ur i n dex ad dr es s es pr ov i d e r eal t i me d a t a r e a d o ut o f s ome i nt e r n al c ou nt er s . t he i n d e x of t h es e c o u nt er s i s s et by 0x 0 5b[ 7: 4] . i n dex 0x 157 0x 1 5 8 0x 1 5 9 0x 15a 0 lvpc n t _ o d d [7:0] l vpcnt _o dd[ 15 : 8 ] lv pc nt _o dd[ 2 3 : 1 6 ] 1 l vpc n t _e vn[7: 0 ] lvp c n t _ evn[ 1 5: 8] lv pcn t _e vn[ 23: 16 ] 2 li v cnt_o d d [ 7 : 0 ] li v cnt _o dd[ 1 1 : 8 ] 3 li v cnt_ e vn[ 7 : 0 ] l i vc n t _e vn[ 1 1: 8] 4 lhp c n t [ 7 :0 ] lh pc n t [ 1 3 : 8 ] l b o v fc [ 7 :0 ] lbovfc [ 1 0 : 8 ] - address bit r/w description reset 0x1f 0 7 - 4 r / w in de x fo r s i m u l a ti on i n i t ia l i z a ti on o f i n te r n a l au t o ca l c u l ation count e r s . 0 : vpcn t [ 23:0 ] p i x e l c o un t e r f o r 1 v s y n c pe ri o d 1 : lvpcn t_od d [ 23 : 0 ] p i x e l coun t e r fo r 1 o d d fi e l d vs y n c pe ri od 2 : lvpcn t_e v n [ 23 : 0 ] p i x e l coun t e r fo r 1 e v en fi e l d v s y n c p e r iod 3 : ivcnt [ 1 1 : 0] l i ne count e r fo r 1 vsy n c p e r iod 4: li v cnt _ o dd [ 1 1: 0] li ne c o u nt er f or 1 o d d f i el d v sy nc p er i o d 5: li v cnt _e v n[ 1 1: 0] li ne c o u nt e r f or 1 e v en f i el d v sy nc p er i od 6 : gocn t [23 : 0 ] pix e l coun te r fr om v s y n c t o the b e g i nn i n g o f ou t p u t d i s p la y 7 : lg o o c n t [23 : 0 ] p i x e l coun te r fr om v s y n c t o the b e g i nn i n g o f ou tpu t d i s p la y ( o dd ) 8 : lg oecnt [ 2 3 : 0 ] pix e l coun t e r fr om vs y n c to the be g i n n i ng o f ou t p u t d i sp l a y (e v e n ) 0000
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 87 r ev. a 0 2 /05 /20 08 3 r/ w 1: force auto calculation to treat input as two fields. 0 2 r/ w 1: force auto calculation to treat input as one field. 0 1 - 0 r/ w su b i n d ex f or t h e ab ov e c ou nt er s , p r ov i di ng by t e w i de d at a r e ad/ w r i t e f r o m / t o 0x 1 f 1. 00: b i t s [ 7: 0] o f t h e c o unt er p oi nt e d by t h e i n d ex 01: b i t s [ 15: 8] o f t he c ou nt er p oi n t e d b y t he i n dex 10: bits [23:16] of the counter pointed by the index 00 address bit r/w description reset 0x1f 1 7 - 0 r/ w d a t a po rt f o r t hose coun te r s m e nti o ned i n i n de x 0 x 1 f 0 . 00h address bit r/w description reset 7 r/ w chi p t e s t u s a ge o nl y . dat a o ut p u t s el ect i o n f or an al o g c i r c ui t t e s t . 0: v dat a 1 : c d at a 0 6 r/ w w h e n s e t , gr ay sc al e d at a r e pl ac e t h e n or m al dat a o ut put t o p an el . t h e c ont e nt of i n d ex 6 1 i s us ed a s t h e f i rst p i x e l da ta . 0 5 r/ w if th i s b i t is se t t o ?1 ? , the s c a l e r ou t p u t is f o r c ed to a l l 0 ? s . 0 4 r/ w r e s e rv ed . 0 3 r/ w r e s e rv ed . 0 2 r/ w r e s e rv ed . 0 1 r/ w s ta rt o s d r o m se lf t e st. 0 0x1f 3 0 r/w st ar t os d ram s e l f t e s t . 0 a ddress bi t r/ w des cription reset 0x1f 4 7 - 0 r bw ymin - a ddress bi t r/ w des cription reset 0x1f 5 7 - 0 r bw ymax - a ddress bi t r/ w des cription reset 0x1f 6 7 - 0 r bw fmin - a ddress bi t r/ w des cription reset 0x1f 7 7 - 0 r bw fmax - a ddress bi t r/ w des cription reset 0x1f 8 7 - 0 r bw btilt - a ddress bi t r/ w des cription reset 0x1f 9 7 - 0 r b wwtilt -
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 88 r ev. a 0 2 /05 /20 08 timi ng co n t roll er confi guration re g i sters 0x175 ? polarity and latch pulse control register bit function r/w description reset 7-5 reserved r/w reserved - 4 clpw r/w 0 : clp width one clock cycle 1: clp width two clock cycle 0 3-0 pol_step r/w polarity signal 16 steps control register 0 0x 176 ? g p io pi xe l c ount hi gh r eg is t er bit function r/w description reset 7-4 reserved r/w reserved - 3-0 gpix_h[11:8] r/w gpix_h[11:8] 0 0x 177 ? g p io pi xe l c ount lo w re g ister bit function r/w description reset 7-0 gpix_l[7:0] r/w gpix_l[7:0] 5a 0x 178 ? g p io li ne cou nt hi gh regi ster bit function r/w description reset 7-4 reserved r/w reserved - 3-0 gline_h[11:8] r/w gline_h[11:8] 0 0x 179 ? g p io li ne cou n t l o w reg i ste r bit function r/w description reset 7-0 gline_l[7:0] r/w gline_l[7:0] 7f 0x 17a ? gpio fra m e c ount reg i ste r bit function r/w description reset 7-3 reserved r/w reserved - 2-0 gframe[2:0] r/w gframe[2:0] 1 0x17b ? tcon and delta rgb misc. control register bit function r/w description reset 7 gpio_con r/w tcon gpio control bit 0 6 line_con r/w d el t a rgb li n e co nt r ol bi t . li n e c o n t r ol f or del t a r g b mo de . f or ex a m pl e, o d d l i ne s t ar t w i th { r ,g ,b ,.. .} a n d e v en li ne st a rt w i th { g , b , r ,...} o r r e v e rs ed . 0 5-4 sync_con r/w d el t a rgb sy nc co nt r ol bi t . t o a dj u st t h e d ot s t ar t p oi nt of del t a rgb mo de . f or ex a m pl e, {r ,g,b,...} o r {g ,b,r ,...} o r {b, r ,g , ...}. 0 3-2 clpsel[1:0] r/w clpsel[1:0] 0 1-0 cspsel[1:0] r/w cspsel[1:0] 0
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 89 r ev. a 0 2 /05 /20 08 0x180 ? output mode control register bit function r/w description relative pin reset 7 g p io_0 r / w lcd pane l si gna l s c o n t r o l 0 : n o rm a l ( s a m e a s b e fo re ) 1 : a l l s i g n a l s and da t a keep z e r o a fte r g p io[0] w a s z e r o . (b e t w e en back l i gh t o ff a nd l c d po w e r o f f ) 0 6 tc c k _ p h r / w tccl k pha s e con t r o l i f reg80 [0] s e t i s h i gh . ( d ua l p i x e l m ode ) 0 : no c l o c k pha s e sh i ft 1 : c l ock pha s e 90 deg r e e s h i ft * * * i t ? s s et r e gb 0[ 3] ( i nv er t cl o c k pol ar i t y ) hi gh a n d t h i s b i t s e t h i g h a l so t h e n tccl k i s 270 deg r e e sh i ft. tc cl k 0 5 ro e _e n r/ w ro e ( r ow dr i v er ) o ut p ut e n abl e 0 : di s a bl e 1 : enab le tr o e 1 4- 1 reserved r/w reserved - 0 d i v_c k r / w o u t p u t m ode s e lection 0 : o n e pi x el d at a o ut p e r t c c lk 1 : tw o pi x el d at a o ut p er t c c lk ( r i s i n g a nd f al l i n g b ot h) tc cl k re set 0x 181 ? disp l a y co ntro l r e g i s t er bi t fun cti on r/w de scri ption re l ative pin reset 7 res er v e d r/ w r es erved - 6 p o l_ co n r/ w t co n polarity swap control bit 0 5 de l t a _li ne _ co n r/w d el t a rgb li n e co nt r ol bi t 0 : t o in te rp o la te e v e n li n e . 1 : t o i nt er p ol at e od d l i n e. 0 4 de l t a _li ne _ en r/ w d el t a rgb i nt er p o l at i o n e n abl e bi t 0 : di s abl e 1 : enab l e p i x e l in t e r p o l a t ion f o r delta r g b m ode. 0 3 r ev_en r / w pi x e l da t a r e v e rse con t r o l 0 : da ta no r e v e rs e (don ?t ca s e tcr e v si gn a l ) 1 : da ta r e v e rs e i f t c r e v si gna l i s h i g h pe ri od tcr e v 0 2 res er v e d r/ w r es er v ed - 1- 0 in v r / w in v e rsi o n m o de sele cti o n 2? b 0 0 : di s abl e 2? b 0 1 : di s abl e 2 ? b10 : l i ne i n v e rsi o n 2? b 1 1 : fr a m e i nv er s i on t ci nv 00
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 90 r ev. a 0 2 /05 /20 08 0x 182 ? disp l a y di recti o n co n t rol registe r bit function r/w description relative pin reset 7- 4 res er v e d r/ w r es er v ed - 3- 2 top _ btm r/ w t o p/ b ot t o m di s pl ay di r ec t i o n s el ect 2 ? b00 : top l o w a ctiv e (no r m a l ) 2? b 0 1 : t o p hi g h a c t i v e ( n or m al ) 2 ? b10 : bo t t o m lo w a c ti v e (f l i p ) 2 ? b11 : bo t t o m h i gh activ e ( f li p ) t r udl t rsp t t rsp b 01 1- 0 lf t_r h t r / w le ft/ r i gh t d i sp l a y d i rec t i o n s e l e ct 2 ? b00 : le ft l o w a c ti v e (no r m a l ) 2 ? b01 : le ft h i gh activ e ( n o r m a l ) 2 ? b10 : r i gh t l o w a c ti v e (mi rro r) 2 ? b11 : r i gh t h i gh a c ti v e ( m irr o r) tclr l tc spl tc spr 01 0 x 1 8 3 ? co nt ro l s i g n a l p o la r i ty s e le ct io n r e gi ste r bit function r/w description relative pin reset 7- 5 res er v e d r/ w r es er v ed - 4 rc k_ p r/ w r ow cl ock p ol ar i t y co nt r ol si g nal tr cl k 1 3 ro e _p r/ w r ow dr iv er out p ut e n abl e si gn al 0 : a c ti v e lo w 1 : a c ti v e h i gh tr o e 1 2 rsp _ p r/ w r ow dr iv er st ar t p ul s e si g n al 0 : a c ti v e lo w 1 : a c ti v e h i gh t rsp t t rsp b 1 1 cl p_ p r/ w c ol u mn dr i v er lat c h p ul s e s i g n al 0 : a c ti v e lo w 1 : a c ti v e h i gh t c lp 1 0 csp _ p r/ w co l u m n d r iv e r s t art pu ls e si gna l 0 : a c ti v e lo w 1 : a c ti v e h i gh tc spl tc spr 1
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 91 r ev. a 0 2 /05 /20 08 0x184 ? control signal generation method register bit function r/w description relative pin reset 7- 6 res er v e d r/ w r es er v ed - 5 pg m _ rc k r/ w r o w dr iv er cl o c k si g nal 0 : thi s i s gene r a t e duri ng hori zon t a l di s p la y enab l e . 1 : it?s ge ne r a t e d t h a t s e t tc on r e g i s t e r add res s 1 a 0 t h ough 1 a 3 . tr cl k 0 4 pgm_r o e r/ w r ow dr iv er out p ut e n abl e si gn al 0 : thi s i s gene r a t e duri ng hori zon t a l di s p la y enab l e . 1 : i t ? s ge ne r a t e d t h a t s e t tc on r e g i s t e r add res s 1 a c th ough 1 a f . als o , th i s i s r e l a tiv e to v e rtica l a c ti v e r e g i s t e r 18c t h ough 1 8 f . tr o e 0 3 pgm_rsp r/ w r ow dr iv er st ar t p ul s e si g n al 0 : t hi s si g nal i m med i at el y ge n e r at e a n d t he n k e e p on e h or i z o nt al pe ri o d ac ti v a ti o n r e ce iv e d fr om v e rti c a l a c ti v e s i gn a l . 1 : i t ? s ge ne r a t e d t h a t s e t tc on r e g i s t e r add res s 1 a 4 t h ough 1 a 7 . als o , th i s i s r e l a tiv e to v e rtica l ba ck p o r ch r e g i st e r b9 . t rsp t t rsp b 0 2 pg m _ c p r/ w c ol u mn dr i v er pol ar i t y si gnal 0 : t hi s si g nal t o ggl i n g w hen h or i z o nt al di s pl ay en a bl e st ar t e d. 1 : i t ? s g en er at e d t hat s et t c o n r egi st er a d dr e ss 19 0 t h o ug h 1 91. t cpo l 0 1 pgm_clp r/ w c ol u mn dr i v er lat c h p ul s e s i g n al 0 : thi s s i gn a l gene r a t e af t e r ho r iz o n ta l di sp l a y e n a b l e done a e v e r y s can l i ne. 1 : i t ? s g en er at e d t hat s et t c o n r egi st er a d dr e ss 19 2 t h ou g h 1 95. t c lp 0 0 pgm_csp r/w column d r iv e r s t art pu ls e si gna l 0 : t hi s si g nal g en er at e af t er hor i z on t al di s pl ay en abl e. 1 : i t ? s ge ne r a t e d t h a t s e t tc on r e g i s t e r add res s 1 9 a t h ough 1 9 d . als o , th i s i s r e l a tiv e to ho ri zon t a l bac k po r c h reg i st e r b 4 . tc spl tc spr 0 0x185 ? inversion si g n al operating p e ri od regi ster bit function r/w description relative pin reset 7-1 reserved r/w reserved - 0 i n v_ sw r/ w in v e rsi o n si gna l (co l um n d r iv e r) wo rki n g pe ri od se l e ction 0 : i n v e rsi o n s i gn al w o r k i n g w i th in d i s p la y enab l e p e r iod 1 : i nv er s i o n si g na l w or k i ng w hol e( di s pl ay en a bl e a n d b l a nki n g t i m e ) pe ri o d t cpo l 0
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 92 r ev. a 0 2 /05 /20 08 0x18a ? special companies lcd module control register bit function r/w description relative pin reset 7-6 reserved r/w reserved - 5- 4 r sp_ w i dth r/ w r ow dr iv er st ar t p ul s e w i dt h ( p e r i o d) s el e ct i o n 0 : o n e hor i z on t al per i o d 1 : t w o hor i z o n t al p er i o d 2 : t hr e e hor i z ont al per i o d 3 : fou r ho rizon t a l pe riod t rsp t t rsp b 00 3-2 reserved r/w reserved - 1- 0 com p any r/ w lcd m odul e co m pan y s e l e c t i o n 2 ? b 0 0 : lg -p h i l i ps lc d m odu l e 2? b0 1 : s h ar p l cd mo d ul e 2 ? b 1 0 , 2 ? b11 : oth e r com pan i e s lcd m odul e tc polp tc poln 10 0x18b ? revv ( t cpo l p) / r e vc ( t cp o l n ) co n t r o l re g i s t er s bit function r/w description relative pin reset 7- 0 r evv_r evc r/ w r evv_r e v c [ 7 :0]; fo r us e w i th sharp p ane l tc polp tc poln 4d 0x 18c ? verti c a l active start hi gh registe r bit function r/w description reset 7-4 reserved r/w reserved - 3-0 v_st[11:8] r/w ver_ash[11:8] 0 0x 18d ? verti c a l active start low register bit function r/w description reset 7-0 v_st[7:0] r/w ver_asl[7:0] 06 0x 18e ? verti cal acti ve end high register bit function r/w description reset 7-4 reserved r/w reserved - 3-0 v_ed[11:8] r/w ver_aeh[11:8] 1 0x 18f ? ve rti cal acti ve end low reg i ste r bit function r/w description reset 7-0 v_ed[7:0] r/w ver_ael[7:0] e2
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 93 r ev. a 0 2 /05 /20 08 column driver chip control signals relative registers 0x190 ? polarity control high register bit function r/w description relative pin reset 7- 4 res er v e d r/ w r es er v ed - 3- 0 cp _s w [ 1 1 : 8] r/ w p r o gr a mma bl e p ol ar i t y per i o d hi g h[ 1 1: 8] v al u e. tc polp tcpoln 2 0x 191 ? p o l arity c ontrol l ow r e gister bit function r/w description relative pin reset 7- 0 cp _s w [ 7 : 0] r/ w p r o gr a mma bl e p ol ar i t y per i o d l o w [ 7: 0] v al ue . tc polp tcpoln d0 0x 192 ? lo a d/ latch p ul s e sta rt hi gh r eg ister bit function r/w description relative pin reset 7- 4 res er v e d r/ w r es er v ed - 3 - 0 cl p_ st [ 11 : 8] r/ w l p_h sh [ 11: 8 ] tclp 2 0x 193 ? loa d/ latch p ul s e sta rt l ow re g ister bi t function r/w description relative pin re set 7- 0 c lp _s t[ 7: 0 ] r / w l p _ h s l [7 :0 ] t c l p d0 0x 194 ? lo a d/ latch p ul s e wi dth hi gh r eg i ste r bit function r/w description relative pin re set 7- 4 res er v e d r/w reserved - 3- 0 c lp _e d [ 11 : 8] r/ w l p_h eh [ 11: 8 ] tclp 0 0x 195 ? lo a d/ latch p ul s e wi dth l ow re g i ster bit function r/w description relative pin re set 7 - 0 cl p_ ed [ 7: 0 ] r / w l p _ h e l [7 :0 ] t c l p 06 0x 19a ? col umn dri v er start pu l s e hi gh regis t er bit function r/w description relative pin re set 7- 4 res er v e d r/w reserved - 3- 0 c sp_s t [ 1 1: 8 ] r/ w sp_ hsh [ 11 : 8 ] tc spl tcspr 0
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 94 r ev. a 0 2 /05 /20 08 0x19b ? column driver start pulse low register bit function r/w description relative pin reset 7- 0 c s p _ s t [7 :0 ] r / w sp_ hsl [ 7 : 0 ] tc spl tc spr c8 0x 19c ? col umn dri v er start pu l s e wi dth hi gh r eg i ste r bit function r/w description relative pin reset 7- 4 res er v e d r/ w r es er v ed - 3- 0 c sp_ed [ 11 : 8 ] r/ w sp_ heh [ 1 1 :8 ] tc spl tcspr 0 0x 19d ? col umn dri v er start pu l s e wi dth low re g i ster bit function r/w description relative pin reset 7- 0 c sp_ed [ 7 : 0 ] r / w sp_ hel [ 7 : 0 ] tc spl tcspr 01 r ow d r i v er c h i p control s i gna l s r e l ati ve regis t ers 0x 1a0 ? clock start pu lse h i g h r eg i ster bit function r/w description relative pin reset 7-4 reserved r/w reserved - 3-0 rsp_st[11:8] r/w sp_hsh[11:8] trclk 0 0x 1a1 ? clock start pu lse l ow r eg i s t er bit function r/w description relative pin reset 7- 0 rsp _s t[ 7 : 0] r/ w sp_ hsl [ 7 : 0 ] tr cl k 0 0x 1a2 ? clock start pu lse wi dth hi gh r eg i ster bit function r/w description relative pin reset 7- 4 res er v e d r/ w r es er v ed - 3- 0 rs p _ e d[ 1 1: 8] r/ w sp_ heh [ 1 1 :8 ] tr cl k 2 0x 1a3 ? clock start pu lse wi dth lo w r eg i ster bit function r/w description relative pin reset 7 - 0 r sp_ed [ 7 : 0 ] r/ w sp_ hel [ 7 : 0 ] tr cl k 30
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 95 r ev. a 0 2 /05 /20 08 0x1a4 ? row start pulse high register bit function r/w description relative pin reset 7-4 reserved r/w reserved - 3- 0 r sp_s t [ 1 1: 8 ] r/ w r sp_v s h [ 11 : 8 ] t rsp t t rsp b 0 0x 1a5 ? row start pulse low regi ste r bit function r/w description relative pin reset 7- 0 r s p _ s t [7 :0 ] r/ w rs p _ vs l [ 7 : 0] t rsp t t rsp b 06 0x 1a6 ? row start pulse w i dth h i gh r eg i ster bit function r/w description relative pin reset 7-4 reserved r/w reserved - 3- 0 r sp_ed [ 11 : 8 ] r/ w r sp_v e h [ 11 : 8 ] t rsp t t rsp b 0 0x 1a7 ? row start pulse w i dth low r eg i ster bit function r/w description relative pin reset 7- 0 r sp_ed [ 7 : 0 ] r/ w rs p _ ve l [ 7 : 0] t rsp t t rsp b 01 0x 1ac ? row o utput enab l e high r eg i ster bit function r/w description relative pin reset 7-4 reserved r/w reserved - 3-0 roe_st[11:8] r/w roe_hsh[11:8] troe 0 0x 1ad ? row o utput enab l e l o w r eg ister bit function r/w description relative pin reset 7-0 roe_st[7:0] r/w roe_hsl[7 :0] troe 0a 0x 1ae ? row o utput enabl e w i dth hi gh re gister bit function r/w description relative pin reset 7-4 reserved r/w reserved - 3-0 roe_ed[11:8] r/w roe_heh[11 :8] troe 0
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 96 r ev. a 0 2 /05 /20 08 0x1af ? row output enable width low register bit function r/w description relative pin reset 7- 0 ro e _e d[ 7 : 0] r/ w ro e _ he l[ 7 : 0] tr o e 36 0x 1b0 ? panel typ e sel ect re gister bit function r/w description relative pin reset 7- 2 res er v e d r/ w r es er v ed - 1 r ev_inv r/ w signa l out p u t s e lec t i o n 0 : tc i n v si gna l ou t p u t s e l e c t 1 : tcr ev o u t pu t se l e ct t ci nv t c re v 1 0 li ne _i nv r/ w an a l o g pane l da t a sw a p p i n g 0 : n o d a ta in ve rs io n 1 : ev er y l i ne d at a i nv er s i o n ro ut go ut bou t tc polp tc poln 0 a na l o g sense bl ock regi ste r 0x 1b1 ? anal og se nse bl ock clo ck g enerati on reg i ster bi t function r/w description reset 7- 5 reserved r/w reserved - 4 bias_ctl r/w bias control 0 3- 0 reserved r/w reserved -
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 97 r ev. a 0 2 /05 /20 08 mc u sfr r e gi s t er 0x 9a ? mcu b ank sel ect r eg ister bit function r/w description reset 7-6 reserved r/w reserved - 5- 0 bank_sel[5:0] r/w bank select for mcu external ram 0 0x9b ? mcu misc. control register bit function r/w description reset 7-6 reserved r/w reserved 00 5- 4 sclk_sel[1:0] r/w spi interface clock selection. 2?b00 div1, 2?b01 div2, 2?b10 div3, 2?b11 div4. 00 3 lowspd r/w spi interface speed control bit. 1?b1 low speed mode. 0 2 host_s1 r/w host interface test mode. 1?b1 force external i2c. 0 1 host_s0 r/w host interface parallel type selection. 1?b0 8051 parallel type. 0 0 dual r/w spi interface dual output mode. 1?b1 dual mode. 0 0x9c ? mcu external timer clock 0 divider high register bit function r/w description reset 7-0 t0_div_h[7:0] r/w t0_div_h[7:0] 0 0x9d ? mcu external timer clock 0 divider low register bit function r/w description reset 7-0 t0_div_l[7:0] r/w t0_div_l[7:0] 90 0x9e ? mcu external timer clock 1 divider high register bit function r/w description reset 7-0 t1_div_h[7:0] r/w t1_div_h[7:0] 0 0x9f ? mcu external timer clock 1 divider low register bit function r/w description reset 7-0 t1_div_l[7:0] r/w t1_div_l[7:0] 90 0x93 ? mcu external timer clock 2 divider high register bit function r/w description reset 7-0 t2_div_h[7:0] r/w t2_div_h[7:0] 0 0x94 ? mcu external timer clock 2 divider low register bit function r/w description reset 7-0 t2_div_l[7:0] r/w t2_div_l[7:0] 90
tw 88 17 digit a l l cd p a ne l processor wit h vid e o deco der, mcu a n d t co n te c h w e l l, i n c. 98 r ev. a 0 2 /05 /20 08 copyright notice this m anu al is cop y righted b y t e chw ell, inc. do not repr oduce, t r a n sf orm t o an y ot her f o rma t , or sen d/t ra nsmit an y part of this do cum entat ion wit h out t h e expr e ss w r itt en perm i ssion of techw ell, i nc. trademark acknowledgment sil i con ima ge, t he silic on i m age l ogo, p anel li nk ? is a regi s t ered tradem ark s o f silic on i m a g e , inc . v esa ? is a registered t r adem a r k of t h e vide o e l ect r oni cs st andards a s sociat ion. all othe r trade m a r k s are th e p r op erty of their resp ecti ve h o l d e r s. disclaimer this d o c um ent pro v id es t echnical i nfo rmat ion for t he us e r . te ch well, inc. re serve s t he ri ght to m odify the inf ormat ion in this doc ume nt as ne cessar y . t he cu st omer shoul d make s ure th at t he y have t he m o st rec ent data she et versio n. t e chwell, inc. holds no re spo nsi bility fo r an y errors that ma y appe ar in t h is document . cu st o m ers sho uld ta ke a ppropriat e a c t i on to ensu r e their u s e of t he p r od uct s d oes not infrin ge up on any patent s. tech w ell, inc. re s pects valid p atent ri ghts of third partie s an d does n ot infrin ge upo n o r a s sist ot hers to inf r inge u po n su ch right s. life support policy techw ell, i nc. prod uct s are not aut horiz ed for use as crit ical comp o ne nt s in lif e suppo rt de vice s or s y st ems. dat a s h ee t revisi on his t ory da t e rev i si on n o t e 12/07/2007 add power consumption information. 01 / 15 / 2008 ad d r ohs la b el . change mcu pin name and description. 02 / 05 / 2008 up da t e v i d eo de cod e r a n d an a l og po w e r in f o r m ation . u p d a te o s d fu n c tio n a l i n fo rm a t io n . u pd at e re gi st er { 0x 00 2, 0x 1b 1} , r e m ov e r e gi s t er { 0x 1b 2 , 0x 1b 3, 0x 1b 4} .
page 50: [1] deleted jaeryon 2/8/2002 7:06:00 pm 0x0d ? vertical scaling register, low (vscale_lo) bit function r/w description reset 7-0 vscale_lo r/w these bits are bit 7 to 0 of the 12-bit vertical scaling ratio register 00h 0x0e ? scaling register, high (scale_hi) bit function r/w description reset 7-4 vscale_hi r/w these bits are bit 11 to 8 of the 12-bit vertical scaling ratio register. 01h 3-0 hscale_hi r/w these bits are bit 11 to 8 of the 12-bit horizontal scaling ratio register. 01h

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